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Merge remote-tracking branch 'qmk 0.17.0' into firmware21

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Drashna Jael're
2022-05-29 15:38:33 -07:00
parent 67f4e5f344 e22a183329
commit 30aac80d5a
337 changed files with 14741 additions and 2516 deletions
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289
platforms/chibios/_pin_defs.h Normal file
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@@ -0,0 +1,289 @@
/* Copyright 2021 QMK
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#pragma once
#if defined(MCU_KINETIS)
// TODO: including this avoids "error: expected identifier before '(' token" errors
// here just to please KINETIS builds...
# include <hal.h>
#endif
#define A0 PAL_LINE(GPIOA, 0)
#define A1 PAL_LINE(GPIOA, 1)
#define A2 PAL_LINE(GPIOA, 2)
#define A3 PAL_LINE(GPIOA, 3)
#define A4 PAL_LINE(GPIOA, 4)
#define A5 PAL_LINE(GPIOA, 5)
#define A6 PAL_LINE(GPIOA, 6)
#define A7 PAL_LINE(GPIOA, 7)
#define A8 PAL_LINE(GPIOA, 8)
#define A9 PAL_LINE(GPIOA, 9)
#define A10 PAL_LINE(GPIOA, 10)
#define A11 PAL_LINE(GPIOA, 11)
#define A12 PAL_LINE(GPIOA, 12)
#define A13 PAL_LINE(GPIOA, 13)
#define A14 PAL_LINE(GPIOA, 14)
#define A15 PAL_LINE(GPIOA, 15)
#define A16 PAL_LINE(GPIOA, 16)
#define A17 PAL_LINE(GPIOA, 17)
#define A18 PAL_LINE(GPIOA, 18)
#define A19 PAL_LINE(GPIOA, 19)
#define A20 PAL_LINE(GPIOA, 20)
#define A21 PAL_LINE(GPIOA, 21)
#define A22 PAL_LINE(GPIOA, 22)
#define A23 PAL_LINE(GPIOA, 23)
#define A24 PAL_LINE(GPIOA, 24)
#define A25 PAL_LINE(GPIOA, 25)
#define A26 PAL_LINE(GPIOA, 26)
#define A27 PAL_LINE(GPIOA, 27)
#define A28 PAL_LINE(GPIOA, 28)
#define A29 PAL_LINE(GPIOA, 29)
#define A30 PAL_LINE(GPIOA, 30)
#define A31 PAL_LINE(GPIOA, 31)
#define A32 PAL_LINE(GPIOA, 32)
#define B0 PAL_LINE(GPIOB, 0)
#define B1 PAL_LINE(GPIOB, 1)
#define B2 PAL_LINE(GPIOB, 2)
#define B3 PAL_LINE(GPIOB, 3)
#define B4 PAL_LINE(GPIOB, 4)
#define B5 PAL_LINE(GPIOB, 5)
#define B6 PAL_LINE(GPIOB, 6)
#define B7 PAL_LINE(GPIOB, 7)
#define B8 PAL_LINE(GPIOB, 8)
#define B9 PAL_LINE(GPIOB, 9)
#define B10 PAL_LINE(GPIOB, 10)
#define B11 PAL_LINE(GPIOB, 11)
#define B12 PAL_LINE(GPIOB, 12)
#define B13 PAL_LINE(GPIOB, 13)
#define B14 PAL_LINE(GPIOB, 14)
#define B15 PAL_LINE(GPIOB, 15)
#define B16 PAL_LINE(GPIOB, 16)
#define B17 PAL_LINE(GPIOB, 17)
#define B18 PAL_LINE(GPIOB, 18)
#define B19 PAL_LINE(GPIOB, 19)
#define B20 PAL_LINE(GPIOB, 20)
#define B21 PAL_LINE(GPIOB, 21)
#define B22 PAL_LINE(GPIOB, 22)
#define B23 PAL_LINE(GPIOB, 23)
#define B24 PAL_LINE(GPIOB, 24)
#define B25 PAL_LINE(GPIOB, 25)
#define B26 PAL_LINE(GPIOB, 26)
#define B27 PAL_LINE(GPIOB, 27)
#define B28 PAL_LINE(GPIOB, 28)
#define B29 PAL_LINE(GPIOB, 29)
#define B30 PAL_LINE(GPIOB, 30)
#define B31 PAL_LINE(GPIOB, 31)
#define B32 PAL_LINE(GPIOB, 32)
#define C0 PAL_LINE(GPIOC, 0)
#define C1 PAL_LINE(GPIOC, 1)
#define C2 PAL_LINE(GPIOC, 2)
#define C3 PAL_LINE(GPIOC, 3)
#define C4 PAL_LINE(GPIOC, 4)
#define C5 PAL_LINE(GPIOC, 5)
#define C6 PAL_LINE(GPIOC, 6)
#define C7 PAL_LINE(GPIOC, 7)
#define C8 PAL_LINE(GPIOC, 8)
#define C9 PAL_LINE(GPIOC, 9)
#define C10 PAL_LINE(GPIOC, 10)
#define C11 PAL_LINE(GPIOC, 11)
#define C12 PAL_LINE(GPIOC, 12)
#define C13 PAL_LINE(GPIOC, 13)
#define C14 PAL_LINE(GPIOC, 14)
#define C15 PAL_LINE(GPIOC, 15)
#define C16 PAL_LINE(GPIOC, 16)
#define C17 PAL_LINE(GPIOC, 17)
#define C18 PAL_LINE(GPIOC, 18)
#define C19 PAL_LINE(GPIOC, 19)
#define C20 PAL_LINE(GPIOC, 20)
#define C21 PAL_LINE(GPIOC, 21)
#define C22 PAL_LINE(GPIOC, 22)
#define C23 PAL_LINE(GPIOC, 23)
#define C24 PAL_LINE(GPIOC, 24)
#define C25 PAL_LINE(GPIOC, 25)
#define C26 PAL_LINE(GPIOC, 26)
#define C27 PAL_LINE(GPIOC, 27)
#define C28 PAL_LINE(GPIOC, 28)
#define C29 PAL_LINE(GPIOC, 29)
#define C30 PAL_LINE(GPIOC, 30)
#define C31 PAL_LINE(GPIOC, 31)
#define C32 PAL_LINE(GPIOC, 32)
#define D0 PAL_LINE(GPIOD, 0)
#define D1 PAL_LINE(GPIOD, 1)
#define D2 PAL_LINE(GPIOD, 2)
#define D3 PAL_LINE(GPIOD, 3)
#define D4 PAL_LINE(GPIOD, 4)
#define D5 PAL_LINE(GPIOD, 5)
#define D6 PAL_LINE(GPIOD, 6)
#define D7 PAL_LINE(GPIOD, 7)
#define D8 PAL_LINE(GPIOD, 8)
#define D9 PAL_LINE(GPIOD, 9)
#define D10 PAL_LINE(GPIOD, 10)
#define D11 PAL_LINE(GPIOD, 11)
#define D12 PAL_LINE(GPIOD, 12)
#define D13 PAL_LINE(GPIOD, 13)
#define D14 PAL_LINE(GPIOD, 14)
#define D15 PAL_LINE(GPIOD, 15)
#define D16 PAL_LINE(GPIOD, 16)
#define D17 PAL_LINE(GPIOD, 17)
#define D18 PAL_LINE(GPIOD, 18)
#define D19 PAL_LINE(GPIOD, 19)
#define D20 PAL_LINE(GPIOD, 20)
#define D21 PAL_LINE(GPIOD, 21)
#define D22 PAL_LINE(GPIOD, 22)
#define D23 PAL_LINE(GPIOD, 23)
#define D24 PAL_LINE(GPIOD, 24)
#define D25 PAL_LINE(GPIOD, 25)
#define D26 PAL_LINE(GPIOD, 26)
#define D27 PAL_LINE(GPIOD, 27)
#define D28 PAL_LINE(GPIOD, 28)
#define D29 PAL_LINE(GPIOD, 29)
#define D30 PAL_LINE(GPIOD, 30)
#define D31 PAL_LINE(GPIOD, 31)
#define D32 PAL_LINE(GPIOD, 32)
#define E0 PAL_LINE(GPIOE, 0)
#define E1 PAL_LINE(GPIOE, 1)
#define E2 PAL_LINE(GPIOE, 2)
#define E3 PAL_LINE(GPIOE, 3)
#define E4 PAL_LINE(GPIOE, 4)
#define E5 PAL_LINE(GPIOE, 5)
#define E6 PAL_LINE(GPIOE, 6)
#define E7 PAL_LINE(GPIOE, 7)
#define E8 PAL_LINE(GPIOE, 8)
#define E9 PAL_LINE(GPIOE, 9)
#define E10 PAL_LINE(GPIOE, 10)
#define E11 PAL_LINE(GPIOE, 11)
#define E12 PAL_LINE(GPIOE, 12)
#define E13 PAL_LINE(GPIOE, 13)
#define E14 PAL_LINE(GPIOE, 14)
#define E15 PAL_LINE(GPIOE, 15)
#define E16 PAL_LINE(GPIOE, 16)
#define E17 PAL_LINE(GPIOE, 17)
#define E18 PAL_LINE(GPIOE, 18)
#define E19 PAL_LINE(GPIOE, 19)
#define E20 PAL_LINE(GPIOE, 20)
#define E21 PAL_LINE(GPIOE, 21)
#define E22 PAL_LINE(GPIOE, 22)
#define E23 PAL_LINE(GPIOE, 23)
#define E24 PAL_LINE(GPIOE, 24)
#define E25 PAL_LINE(GPIOE, 25)
#define E26 PAL_LINE(GPIOE, 26)
#define E27 PAL_LINE(GPIOE, 27)
#define E28 PAL_LINE(GPIOE, 28)
#define E29 PAL_LINE(GPIOE, 29)
#define E30 PAL_LINE(GPIOE, 30)
#define E31 PAL_LINE(GPIOE, 31)
#define E32 PAL_LINE(GPIOE, 32)
#define F0 PAL_LINE(GPIOF, 0)
#define F1 PAL_LINE(GPIOF, 1)
#define F2 PAL_LINE(GPIOF, 2)
#define F3 PAL_LINE(GPIOF, 3)
#define F4 PAL_LINE(GPIOF, 4)
#define F5 PAL_LINE(GPIOF, 5)
#define F6 PAL_LINE(GPIOF, 6)
#define F7 PAL_LINE(GPIOF, 7)
#define F8 PAL_LINE(GPIOF, 8)
#define F9 PAL_LINE(GPIOF, 9)
#define F10 PAL_LINE(GPIOF, 10)
#define F11 PAL_LINE(GPIOF, 11)
#define F12 PAL_LINE(GPIOF, 12)
#define F13 PAL_LINE(GPIOF, 13)
#define F14 PAL_LINE(GPIOF, 14)
#define F15 PAL_LINE(GPIOF, 15)
#define G0 PAL_LINE(GPIOG, 0)
#define G1 PAL_LINE(GPIOG, 1)
#define G2 PAL_LINE(GPIOG, 2)
#define G3 PAL_LINE(GPIOG, 3)
#define G4 PAL_LINE(GPIOG, 4)
#define G5 PAL_LINE(GPIOG, 5)
#define G6 PAL_LINE(GPIOG, 6)
#define G7 PAL_LINE(GPIOG, 7)
#define G8 PAL_LINE(GPIOG, 8)
#define G9 PAL_LINE(GPIOG, 9)
#define G10 PAL_LINE(GPIOG, 10)
#define G11 PAL_LINE(GPIOG, 11)
#define G12 PAL_LINE(GPIOG, 12)
#define G13 PAL_LINE(GPIOG, 13)
#define G14 PAL_LINE(GPIOG, 14)
#define G15 PAL_LINE(GPIOG, 15)
#define H0 PAL_LINE(GPIOH, 0)
#define H1 PAL_LINE(GPIOH, 1)
#define H2 PAL_LINE(GPIOH, 2)
#define H3 PAL_LINE(GPIOH, 3)
#define H4 PAL_LINE(GPIOH, 4)
#define H5 PAL_LINE(GPIOH, 5)
#define H6 PAL_LINE(GPIOH, 6)
#define H7 PAL_LINE(GPIOH, 7)
#define H8 PAL_LINE(GPIOH, 8)
#define H9 PAL_LINE(GPIOH, 9)
#define H10 PAL_LINE(GPIOH, 10)
#define H11 PAL_LINE(GPIOH, 11)
#define H12 PAL_LINE(GPIOH, 12)
#define H13 PAL_LINE(GPIOH, 13)
#define H14 PAL_LINE(GPIOH, 14)
#define H15 PAL_LINE(GPIOH, 15)
#define I0 PAL_LINE(GPIOI, 0)
#define I1 PAL_LINE(GPIOI, 1)
#define I2 PAL_LINE(GPIOI, 2)
#define I3 PAL_LINE(GPIOI, 3)
#define I4 PAL_LINE(GPIOI, 4)
#define I5 PAL_LINE(GPIOI, 5)
#define I6 PAL_LINE(GPIOI, 6)
#define I7 PAL_LINE(GPIOI, 7)
#define I8 PAL_LINE(GPIOI, 8)
#define I9 PAL_LINE(GPIOI, 9)
#define I10 PAL_LINE(GPIOI, 10)
#define I11 PAL_LINE(GPIOI, 11)
#define I12 PAL_LINE(GPIOI, 12)
#define I13 PAL_LINE(GPIOI, 13)
#define I14 PAL_LINE(GPIOI, 14)
#define I15 PAL_LINE(GPIOI, 15)
#define J0 PAL_LINE(GPIOJ, 0)
#define J1 PAL_LINE(GPIOJ, 1)
#define J2 PAL_LINE(GPIOJ, 2)
#define J3 PAL_LINE(GPIOJ, 3)
#define J4 PAL_LINE(GPIOJ, 4)
#define J5 PAL_LINE(GPIOJ, 5)
#define J6 PAL_LINE(GPIOJ, 6)
#define J7 PAL_LINE(GPIOJ, 7)
#define J8 PAL_LINE(GPIOJ, 8)
#define J9 PAL_LINE(GPIOJ, 9)
#define J10 PAL_LINE(GPIOJ, 10)
#define J11 PAL_LINE(GPIOJ, 11)
#define J12 PAL_LINE(GPIOJ, 12)
#define J13 PAL_LINE(GPIOJ, 13)
#define J14 PAL_LINE(GPIOJ, 14)
#define J15 PAL_LINE(GPIOJ, 15)
// Keyboards can `#define KEYBOARD_REQUIRES_GPIOK` if they need to access GPIO-K pins. These conflict with a whole
// bunch of layout definitions, so it's intentionally left out unless absolutely required -- in that case, the
// keyboard designer should use a different symbol when defining their layout macros.
#ifdef KEYBOARD_REQUIRES_GPIOK
# define K0 PAL_LINE(GPIOK, 0)
# define K1 PAL_LINE(GPIOK, 1)
# define K2 PAL_LINE(GPIOK, 2)
# define K3 PAL_LINE(GPIOK, 3)
# define K4 PAL_LINE(GPIOK, 4)
# define K5 PAL_LINE(GPIOK, 5)
# define K6 PAL_LINE(GPIOK, 6)
# define K7 PAL_LINE(GPIOK, 7)
# define K8 PAL_LINE(GPIOK, 8)
# define K9 PAL_LINE(GPIOK, 9)
# define K10 PAL_LINE(GPIOK, 10)
# define K11 PAL_LINE(GPIOK, 11)
# define K12 PAL_LINE(GPIOK, 12)
# define K13 PAL_LINE(GPIOK, 13)
# define K14 PAL_LINE(GPIOK, 14)
# define K15 PAL_LINE(GPIOK, 15)
#endif

57
platforms/chibios/boards/BLACKPILL_STM32_F401/configs/board.h
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@@ -17,4 +17,61 @@
#include_next "board.h"
// Force B9 as input to align with qmk defaults
#undef VAL_GPIOB_MODER
#define VAL_GPIOB_MODER (PIN_MODE_INPUT(GPIOB_PIN0) | \
PIN_MODE_INPUT(GPIOB_PIN1) | \
PIN_MODE_INPUT(GPIOB_PIN2) | \
PIN_MODE_ALTERNATE(GPIOB_SWO) | \
PIN_MODE_INPUT(GPIOB_PIN4) | \
PIN_MODE_INPUT(GPIOB_PIN5) | \
PIN_MODE_INPUT(GPIOB_LSM303DLHC_SCL) | \
PIN_MODE_INPUT(GPIOB_PIN7) | \
PIN_MODE_INPUT(GPIOB_PIN8) | \
PIN_MODE_INPUT(GPIOB_LSM303DLHC_SDA) | \
PIN_MODE_ALTERNATE(GPIOB_MP45DT02_CLK_IN) |\
PIN_MODE_INPUT(GPIOB_PIN11) | \
PIN_MODE_INPUT(GPIOB_PIN12) | \
PIN_MODE_INPUT(GPIOB_PIN13) | \
PIN_MODE_INPUT(GPIOB_PIN14) | \
PIN_MODE_INPUT(GPIOB_PIN15))
#undef VAL_GPIOB_PUPDR
#define VAL_GPIOB_PUPDR (PIN_PUPDR_PULLUP(GPIOB_PIN0) | \
PIN_PUPDR_PULLUP(GPIOB_PIN1) | \
PIN_PUPDR_PULLUP(GPIOB_PIN2) | \
PIN_PUPDR_PULLUP(GPIOB_SWO) | \
PIN_PUPDR_PULLUP(GPIOB_PIN4) | \
PIN_PUPDR_PULLUP(GPIOB_PIN5) | \
PIN_PUPDR_PULLUP(GPIOB_LSM303DLHC_SCL) |\
PIN_PUPDR_PULLUP(GPIOB_PIN7) | \
PIN_PUPDR_PULLUP(GPIOB_PIN8) | \
PIN_PUPDR_PULLUP(GPIOB_LSM303DLHC_SDA) |\
PIN_PUPDR_FLOATING(GPIOB_MP45DT02_CLK_IN) |\
PIN_PUPDR_PULLUP(GPIOB_PIN11) | \
PIN_PUPDR_PULLUP(GPIOB_PIN12) | \
PIN_PUPDR_PULLUP(GPIOB_PIN13) | \
PIN_PUPDR_PULLUP(GPIOB_PIN14) | \
PIN_PUPDR_PULLUP(GPIOB_PIN15))
#undef VAL_GPIOB_AFRL
#define VAL_GPIOB_AFRL (PIN_AFIO_AF(GPIOB_PIN0, 0U) | \
PIN_AFIO_AF(GPIOB_PIN1, 0U) | \
PIN_AFIO_AF(GPIOB_PIN2, 0U) | \
PIN_AFIO_AF(GPIOB_SWO, 0U) | \
PIN_AFIO_AF(GPIOB_PIN4, 0U) | \
PIN_AFIO_AF(GPIOB_PIN5, 0U) | \
PIN_AFIO_AF(GPIOB_LSM303DLHC_SCL, 0) | \
PIN_AFIO_AF(GPIOB_PIN7, 0U))
#undef VAL_GPIOB_AFRH
#define VAL_GPIOB_AFRH (PIN_AFIO_AF(GPIOB_PIN8, 0U) | \
PIN_AFIO_AF(GPIOB_LSM303DLHC_SDA, 0) | \
PIN_AFIO_AF(GPIOB_MP45DT02_CLK_IN, 5U) |\
PIN_AFIO_AF(GPIOB_PIN11, 0U) | \
PIN_AFIO_AF(GPIOB_PIN12, 0U) | \
PIN_AFIO_AF(GPIOB_PIN13, 0U) | \
PIN_AFIO_AF(GPIOB_PIN14, 0U) | \
PIN_AFIO_AF(GPIOB_PIN15, 0U))
#undef STM32_HSE_BYPASS

3
platforms/chibios/boards/GENERIC_STM32_F303XC/configs/mcuconf.h
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@@ -1,5 +1,5 @@
/*
ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
@@ -186,7 +186,6 @@
/*
* PWM driver system settings.
*/
#define STM32_PWM_USE_ADVANCED FALSE
#define STM32_PWM_USE_TIM1 FALSE
#define STM32_PWM_USE_TIM2 FALSE
#define STM32_PWM_USE_TIM3 FALSE

9
platforms/chibios/boards/GENERIC_STM32_F401XC/board/board.mk Normal file
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@@ -0,0 +1,9 @@
# List of all the board related files.
BOARDSRC = $(CHIBIOS)/os/hal/boards/ST_STM32F401C_DISCOVERY/board.c
# Required include directories
BOARDINC = $(CHIBIOS)/os/hal/boards/ST_STM32F401C_DISCOVERY
# Shared variables
ALLCSRC += $(BOARDSRC)
ALLINC += $(BOARDINC)

77
platforms/chibios/boards/GENERIC_STM32_F401XC/configs/board.h Normal file
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@@ -0,0 +1,77 @@
/* Copyright 2020 Nick Brassel (tzarc)
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <https://www.gnu.org/licenses/>.
*/
#pragma once
#include_next "board.h"
// Force B9 as input to align with qmk defaults
#undef VAL_GPIOB_MODER
#define VAL_GPIOB_MODER (PIN_MODE_INPUT(GPIOB_PIN0) | \
PIN_MODE_INPUT(GPIOB_PIN1) | \
PIN_MODE_INPUT(GPIOB_PIN2) | \
PIN_MODE_ALTERNATE(GPIOB_SWO) | \
PIN_MODE_INPUT(GPIOB_PIN4) | \
PIN_MODE_INPUT(GPIOB_PIN5) | \
PIN_MODE_INPUT(GPIOB_LSM303DLHC_SCL) | \
PIN_MODE_INPUT(GPIOB_PIN7) | \
PIN_MODE_INPUT(GPIOB_PIN8) | \
PIN_MODE_INPUT(GPIOB_LSM303DLHC_SDA) | \
PIN_MODE_ALTERNATE(GPIOB_MP45DT02_CLK_IN) |\
PIN_MODE_INPUT(GPIOB_PIN11) | \
PIN_MODE_INPUT(GPIOB_PIN12) | \
PIN_MODE_INPUT(GPIOB_PIN13) | \
PIN_MODE_INPUT(GPIOB_PIN14) | \
PIN_MODE_INPUT(GPIOB_PIN15))
#undef VAL_GPIOB_PUPDR
#define VAL_GPIOB_PUPDR (PIN_PUPDR_PULLUP(GPIOB_PIN0) | \
PIN_PUPDR_PULLUP(GPIOB_PIN1) | \
PIN_PUPDR_PULLUP(GPIOB_PIN2) | \
PIN_PUPDR_PULLUP(GPIOB_SWO) | \
PIN_PUPDR_PULLUP(GPIOB_PIN4) | \
PIN_PUPDR_PULLUP(GPIOB_PIN5) | \
PIN_PUPDR_PULLUP(GPIOB_LSM303DLHC_SCL) |\
PIN_PUPDR_PULLUP(GPIOB_PIN7) | \
PIN_PUPDR_PULLUP(GPIOB_PIN8) | \
PIN_PUPDR_PULLUP(GPIOB_LSM303DLHC_SDA) |\
PIN_PUPDR_FLOATING(GPIOB_MP45DT02_CLK_IN) |\
PIN_PUPDR_PULLUP(GPIOB_PIN11) | \
PIN_PUPDR_PULLUP(GPIOB_PIN12) | \
PIN_PUPDR_PULLUP(GPIOB_PIN13) | \
PIN_PUPDR_PULLUP(GPIOB_PIN14) | \
PIN_PUPDR_PULLUP(GPIOB_PIN15))
#undef VAL_GPIOB_AFRL
#define VAL_GPIOB_AFRL (PIN_AFIO_AF(GPIOB_PIN0, 0U) | \
PIN_AFIO_AF(GPIOB_PIN1, 0U) | \
PIN_AFIO_AF(GPIOB_PIN2, 0U) | \
PIN_AFIO_AF(GPIOB_SWO, 0U) | \
PIN_AFIO_AF(GPIOB_PIN4, 0U) | \
PIN_AFIO_AF(GPIOB_PIN5, 0U) | \
PIN_AFIO_AF(GPIOB_LSM303DLHC_SCL, 0) | \
PIN_AFIO_AF(GPIOB_PIN7, 0U))
#undef VAL_GPIOB_AFRH
#define VAL_GPIOB_AFRH (PIN_AFIO_AF(GPIOB_PIN8, 0U) | \
PIN_AFIO_AF(GPIOB_LSM303DLHC_SDA, 0) | \
PIN_AFIO_AF(GPIOB_MP45DT02_CLK_IN, 5U) |\
PIN_AFIO_AF(GPIOB_PIN11, 0U) | \
PIN_AFIO_AF(GPIOB_PIN12, 0U) | \
PIN_AFIO_AF(GPIOB_PIN13, 0U) | \
PIN_AFIO_AF(GPIOB_PIN14, 0U) | \
PIN_AFIO_AF(GPIOB_PIN15, 0U))
#undef STM32_HSE_BYPASS

22
platforms/chibios/boards/GENERIC_STM32_F401XC/configs/config.h Normal file
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@@ -0,0 +1,22 @@
/* Copyright 2020 Nick Brassel (tzarc)
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <https://www.gnu.org/licenses/>.
*/
#pragma once
#define BOARD_OTG_NOVBUSSENS 1
#ifndef EARLY_INIT_PERFORM_BOOTLOADER_JUMP
# define EARLY_INIT_PERFORM_BOOTLOADER_JUMP TRUE
#endif

244
platforms/chibios/boards/GENERIC_STM32_F401XC/configs/mcuconf.h Normal file
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@@ -0,0 +1,244 @@
/*
ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
#ifndef MCUCONF_H
#define MCUCONF_H
/*
* STM32F4xx drivers configuration.
* The following settings override the default settings present in
* the various device driver implementation headers.
* Note that the settings for each driver only have effect if the whole
* driver is enabled in halconf.h.
*
* IRQ priorities:
* 15...0 Lowest...Highest.
*
* DMA priorities:
* 0...3 Lowest...Highest.
*/
#define STM32F4xx_MCUCONF
#define STM32F401_MCUCONF
/*
* HAL driver system settings.
*/
#define STM32_NO_INIT FALSE
#define STM32_PVD_ENABLE FALSE
#define STM32_PLS STM32_PLS_LEV0
#define STM32_BKPRAM_ENABLE FALSE
#define STM32_HSI_ENABLED TRUE
#define STM32_LSI_ENABLED TRUE
#define STM32_HSE_ENABLED TRUE
#define STM32_LSE_ENABLED FALSE
#define STM32_CLOCK48_REQUIRED TRUE
#define STM32_SW STM32_SW_PLL
#define STM32_PLLSRC STM32_PLLSRC_HSE
#define STM32_PLLM_VALUE 4
#define STM32_PLLN_VALUE 168
#define STM32_PLLP_VALUE 4
#define STM32_PLLQ_VALUE 7
#define STM32_HPRE STM32_HPRE_DIV1
#define STM32_PPRE1 STM32_PPRE1_DIV2
#define STM32_PPRE2 STM32_PPRE2_DIV1
#define STM32_RTCSEL STM32_RTCSEL_LSI
#define STM32_RTCPRE_VALUE 8
#define STM32_MCO1SEL STM32_MCO1SEL_HSI
#define STM32_MCO1PRE STM32_MCO1PRE_DIV1
#define STM32_MCO2SEL STM32_MCO2SEL_SYSCLK
#define STM32_MCO2PRE STM32_MCO2PRE_DIV5
#define STM32_I2SSRC STM32_I2SSRC_CKIN
#define STM32_PLLI2SN_VALUE 192
#define STM32_PLLI2SR_VALUE 5
/*
* IRQ system settings.
*/
#define STM32_IRQ_EXTI0_PRIORITY 6
#define STM32_IRQ_EXTI1_PRIORITY 6
#define STM32_IRQ_EXTI2_PRIORITY 6
#define STM32_IRQ_EXTI3_PRIORITY 6
#define STM32_IRQ_EXTI4_PRIORITY 6
#define STM32_IRQ_EXTI5_9_PRIORITY 6
#define STM32_IRQ_EXTI10_15_PRIORITY 6
#define STM32_IRQ_EXTI16_PRIORITY 6
#define STM32_IRQ_EXTI17_PRIORITY 15
#define STM32_IRQ_EXTI18_PRIORITY 6
#define STM32_IRQ_EXTI19_PRIORITY 6
#define STM32_IRQ_EXTI20_PRIORITY 6
#define STM32_IRQ_EXTI21_PRIORITY 15
#define STM32_IRQ_EXTI22_PRIORITY 15
#define STM32_IRQ_TIM1_BRK_TIM9_PRIORITY 7
#define STM32_IRQ_TIM1_UP_TIM10_PRIORITY 7
#define STM32_IRQ_TIM1_TRGCO_TIM11_PRIORITY 7
#define STM32_IRQ_TIM1_CC_PRIORITY 7
#define STM32_IRQ_TIM2_PRIORITY 7
#define STM32_IRQ_TIM3_PRIORITY 7
#define STM32_IRQ_TIM4_PRIORITY 7
#define STM32_IRQ_TIM5_PRIORITY 7
#define STM32_IRQ_USART1_PRIORITY 12
#define STM32_IRQ_USART2_PRIORITY 12
#define STM32_IRQ_USART6_PRIORITY 12
/*
* ADC driver system settings.
*/
#define STM32_ADC_ADCPRE ADC_CCR_ADCPRE_DIV4
#define STM32_ADC_USE_ADC1 FALSE
#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(2, 4)
#define STM32_ADC_ADC1_DMA_PRIORITY 2
#define STM32_ADC_IRQ_PRIORITY 6
#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 6
/*
* GPT driver system settings.
*/
#define STM32_GPT_USE_TIM1 FALSE
#define STM32_GPT_USE_TIM2 FALSE
#define STM32_GPT_USE_TIM3 FALSE
#define STM32_GPT_USE_TIM4 FALSE
#define STM32_GPT_USE_TIM5 FALSE
#define STM32_GPT_USE_TIM9 FALSE
#define STM32_GPT_USE_TIM10 FALSE
#define STM32_GPT_USE_TIM11 FALSE
/*
* I2C driver system settings.
*/
#define STM32_I2C_USE_I2C1 FALSE
#define STM32_I2C_USE_I2C2 FALSE
#define STM32_I2C_USE_I2C3 FALSE
#define STM32_I2C_BUSY_TIMEOUT 50
#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0)
#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
#define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
#define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
#define STM32_I2C_I2C1_IRQ_PRIORITY 5
#define STM32_I2C_I2C2_IRQ_PRIORITY 5
#define STM32_I2C_I2C3_IRQ_PRIORITY 5
#define STM32_I2C_I2C1_DMA_PRIORITY 3
#define STM32_I2C_I2C2_DMA_PRIORITY 3
#define STM32_I2C_I2C3_DMA_PRIORITY 3
#define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure")
/*
* I2S driver system settings.
*/
#define STM32_I2S_USE_SPI2 FALSE
#define STM32_I2S_USE_SPI3 FALSE
#define STM32_I2S_SPI2_IRQ_PRIORITY 10
#define STM32_I2S_SPI3_IRQ_PRIORITY 10
#define STM32_I2S_SPI2_DMA_PRIORITY 1
#define STM32_I2S_SPI3_DMA_PRIORITY 1
#define STM32_I2S_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
#define STM32_I2S_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
#define STM32_I2S_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0)
#define STM32_I2S_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
#define STM32_I2S_DMA_ERROR_HOOK(i2sp) osalSysHalt("DMA failure")
/*
* ICU driver system settings.
*/
#define STM32_ICU_USE_TIM1 FALSE
#define STM32_ICU_USE_TIM2 FALSE
#define STM32_ICU_USE_TIM3 FALSE
#define STM32_ICU_USE_TIM4 FALSE
#define STM32_ICU_USE_TIM5 FALSE
#define STM32_ICU_USE_TIM9 FALSE
#define STM32_ICU_USE_TIM10 FALSE
#define STM32_ICU_USE_TIM11 FALSE
/*
* PWM driver system settings.
*/
#define STM32_PWM_USE_TIM1 FALSE
#define STM32_PWM_USE_TIM2 FALSE
#define STM32_PWM_USE_TIM3 FALSE
#define STM32_PWM_USE_TIM4 FALSE
#define STM32_PWM_USE_TIM5 FALSE
#define STM32_PWM_USE_TIM9 FALSE
#define STM32_PWM_USE_TIM10 FALSE
#define STM32_PWM_USE_TIM11 FALSE
/*
* SERIAL driver system settings.
*/
#define STM32_SERIAL_USE_USART1 FALSE
#define STM32_SERIAL_USE_USART2 FALSE
#define STM32_SERIAL_USE_USART6 FALSE
/*
* SPI driver system settings.
*/
#define STM32_SPI_USE_SPI1 FALSE
#define STM32_SPI_USE_SPI2 FALSE
#define STM32_SPI_USE_SPI3 FALSE
#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0)
#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3)
#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0)
#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
#define STM32_SPI_SPI1_DMA_PRIORITY 1
#define STM32_SPI_SPI2_DMA_PRIORITY 1
#define STM32_SPI_SPI3_DMA_PRIORITY 1
#define STM32_SPI_SPI1_IRQ_PRIORITY 10
#define STM32_SPI_SPI2_IRQ_PRIORITY 10
#define STM32_SPI_SPI3_IRQ_PRIORITY 10
#define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure")
/*
* ST driver system settings.
*/
#define STM32_ST_IRQ_PRIORITY 8
#define STM32_ST_USE_TIMER 2
/*
* UART driver system settings.
*/
#define STM32_UART_USE_USART1 FALSE
#define STM32_UART_USE_USART2 FALSE
#define STM32_UART_USE_USART6 FALSE
#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5)
#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
#define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
#define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
#define STM32_UART_USART1_DMA_PRIORITY 0
#define STM32_UART_USART2_DMA_PRIORITY 0
#define STM32_UART_USART6_DMA_PRIORITY 0
#define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure")
/*
* USB driver system settings.
*/
#define STM32_USB_USE_OTG1 TRUE
#define STM32_USB_OTG1_IRQ_PRIORITY 14
#define STM32_USB_OTG1_RX_FIFO_SIZE 512
#define STM32_USB_HOST_WAKEUP_DURATION 2
/*
* WDG driver system settings.
*/
#define STM32_WDG_USE_IWDG FALSE
#endif /* MCUCONF_H */

75
platforms/chibios/boards/GENERIC_STM32_F405XG/configs/mcuconf.h
View File

@@ -1,5 +1,5 @@
/*
ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
@@ -86,6 +86,28 @@
#define STM32_IRQ_EXTI21_PRIORITY 15
#define STM32_IRQ_EXTI22_PRIORITY 15
#define STM32_IRQ_TIM1_BRK_TIM9_PRIORITY 7
#define STM32_IRQ_TIM1_UP_TIM10_PRIORITY 7
#define STM32_IRQ_TIM1_TRGCO_TIM11_PRIORITY 7
#define STM32_IRQ_TIM1_CC_PRIORITY 7
#define STM32_IRQ_TIM2_PRIORITY 7
#define STM32_IRQ_TIM3_PRIORITY 7
#define STM32_IRQ_TIM4_PRIORITY 7
#define STM32_IRQ_TIM5_PRIORITY 7
#define STM32_IRQ_TIM6_PRIORITY 7
#define STM32_IRQ_TIM7_PRIORITY 7
#define STM32_IRQ_TIM8_BRK_TIM12_PRIORITY 7
#define STM32_IRQ_TIM8_UP_TIM13_PRIORITY 7
#define STM32_IRQ_TIM8_TRGCO_TIM14_PRIORITY 7
#define STM32_IRQ_TIM8_CC_PRIORITY 7
#define STM32_IRQ_USART1_PRIORITY 12
#define STM32_IRQ_USART2_PRIORITY 12
#define STM32_IRQ_USART3_PRIORITY 12
#define STM32_IRQ_UART4_PRIORITY 12
#define STM32_IRQ_UART5_PRIORITY 12
#define STM32_IRQ_USART6_PRIORITY 12
/*
* ADC driver system settings.
*/
@@ -137,21 +159,11 @@
#define STM32_GPT_USE_TIM7 FALSE
#define STM32_GPT_USE_TIM8 FALSE
#define STM32_GPT_USE_TIM9 FALSE
#define STM32_GPT_USE_TIM10 FALSE
#define STM32_GPT_USE_TIM11 FALSE
#define STM32_GPT_USE_TIM12 FALSE
#define STM32_GPT_USE_TIM13 FALSE
#define STM32_GPT_USE_TIM14 FALSE
#define STM32_GPT_TIM1_IRQ_PRIORITY 7
#define STM32_GPT_TIM2_IRQ_PRIORITY 7
#define STM32_GPT_TIM3_IRQ_PRIORITY 7
#define STM32_GPT_TIM4_IRQ_PRIORITY 7
#define STM32_GPT_TIM5_IRQ_PRIORITY 7
#define STM32_GPT_TIM6_IRQ_PRIORITY 7
#define STM32_GPT_TIM7_IRQ_PRIORITY 7
#define STM32_GPT_TIM8_IRQ_PRIORITY 7
#define STM32_GPT_TIM9_IRQ_PRIORITY 7
#define STM32_GPT_TIM11_IRQ_PRIORITY 7
#define STM32_GPT_TIM12_IRQ_PRIORITY 7
#define STM32_GPT_TIM14_IRQ_PRIORITY 7
/*
* I2C driver system settings.
@@ -199,13 +211,11 @@
#define STM32_ICU_USE_TIM5 FALSE
#define STM32_ICU_USE_TIM8 FALSE
#define STM32_ICU_USE_TIM9 FALSE
#define STM32_ICU_TIM1_IRQ_PRIORITY 7
#define STM32_ICU_TIM2_IRQ_PRIORITY 7
#define STM32_ICU_TIM3_IRQ_PRIORITY 7
#define STM32_ICU_TIM4_IRQ_PRIORITY 7
#define STM32_ICU_TIM5_IRQ_PRIORITY 7
#define STM32_ICU_TIM8_IRQ_PRIORITY 7
#define STM32_ICU_TIM9_IRQ_PRIORITY 7
#define STM32_ICU_USE_TIM10 FALSE
#define STM32_ICU_USE_TIM11 FALSE
#define STM32_ICU_USE_TIM12 FALSE
#define STM32_ICU_USE_TIM13 FALSE
#define STM32_ICU_USE_TIM14 FALSE
/*
* MAC driver system settings.
@@ -221,7 +231,6 @@
/*
* PWM driver system settings.
*/
#define STM32_PWM_USE_ADVANCED FALSE
#define STM32_PWM_USE_TIM1 FALSE
#define STM32_PWM_USE_TIM2 FALSE
#define STM32_PWM_USE_TIM3 FALSE
@@ -229,13 +238,11 @@
#define STM32_PWM_USE_TIM5 FALSE
#define STM32_PWM_USE_TIM8 FALSE
#define STM32_PWM_USE_TIM9 FALSE
#define STM32_PWM_TIM1_IRQ_PRIORITY 7
#define STM32_PWM_TIM2_IRQ_PRIORITY 7
#define STM32_PWM_TIM3_IRQ_PRIORITY 7
#define STM32_PWM_TIM4_IRQ_PRIORITY 7
#define STM32_PWM_TIM5_IRQ_PRIORITY 7
#define STM32_PWM_TIM8_IRQ_PRIORITY 7
#define STM32_PWM_TIM9_IRQ_PRIORITY 7
#define STM32_PWM_USE_TIM10 FALSE
#define STM32_PWM_USE_TIM11 FALSE
#define STM32_PWM_USE_TIM12 FALSE
#define STM32_PWM_USE_TIM13 FALSE
#define STM32_PWM_USE_TIM14 FALSE
/*
* RTC driver system settings.
@@ -265,12 +272,6 @@
#define STM32_SERIAL_USE_UART4 FALSE
#define STM32_SERIAL_USE_UART5 FALSE
#define STM32_SERIAL_USE_USART6 FALSE
#define STM32_SERIAL_USART1_PRIORITY 12
#define STM32_SERIAL_USART2_PRIORITY 12
#define STM32_SERIAL_USART3_PRIORITY 12
#define STM32_SERIAL_UART4_PRIORITY 12
#define STM32_SERIAL_UART5_PRIORITY 12
#define STM32_SERIAL_USART6_PRIORITY 12
/*
* SPI driver system settings.
@@ -319,12 +320,6 @@
#define STM32_UART_UART5_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
#define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
#define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
#define STM32_UART_USART1_IRQ_PRIORITY 12
#define STM32_UART_USART2_IRQ_PRIORITY 12
#define STM32_UART_USART3_IRQ_PRIORITY 12
#define STM32_UART_UART4_IRQ_PRIORITY 12
#define STM32_UART_UART5_IRQ_PRIORITY 12
#define STM32_UART_USART6_IRQ_PRIORITY 12
#define STM32_UART_USART1_DMA_PRIORITY 0
#define STM32_UART_USART2_DMA_PRIORITY 0
#define STM32_UART_USART3_DMA_PRIORITY 0

75
platforms/chibios/boards/GENERIC_STM32_F407XE/configs/mcuconf.h
View File

@@ -1,5 +1,5 @@
/*
ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
@@ -86,6 +86,28 @@
#define STM32_IRQ_EXTI21_PRIORITY 15
#define STM32_IRQ_EXTI22_PRIORITY 15
#define STM32_IRQ_TIM1_BRK_TIM9_PRIORITY 7
#define STM32_IRQ_TIM1_UP_TIM10_PRIORITY 7
#define STM32_IRQ_TIM1_TRGCO_TIM11_PRIORITY 7
#define STM32_IRQ_TIM1_CC_PRIORITY 7
#define STM32_IRQ_TIM2_PRIORITY 7
#define STM32_IRQ_TIM3_PRIORITY 7
#define STM32_IRQ_TIM4_PRIORITY 7
#define STM32_IRQ_TIM5_PRIORITY 7
#define STM32_IRQ_TIM6_PRIORITY 7
#define STM32_IRQ_TIM7_PRIORITY 7
#define STM32_IRQ_TIM8_BRK_TIM12_PRIORITY 7
#define STM32_IRQ_TIM8_UP_TIM13_PRIORITY 7
#define STM32_IRQ_TIM8_TRGCO_TIM14_PRIORITY 7
#define STM32_IRQ_TIM8_CC_PRIORITY 7
#define STM32_IRQ_USART1_PRIORITY 12
#define STM32_IRQ_USART2_PRIORITY 12
#define STM32_IRQ_USART3_PRIORITY 12
#define STM32_IRQ_UART4_PRIORITY 12
#define STM32_IRQ_UART5_PRIORITY 12
#define STM32_IRQ_USART6_PRIORITY 12
/*
* ADC driver system settings.
*/
@@ -137,21 +159,11 @@
#define STM32_GPT_USE_TIM7 FALSE
#define STM32_GPT_USE_TIM8 FALSE
#define STM32_GPT_USE_TIM9 FALSE
#define STM32_GPT_USE_TIM10 FALSE
#define STM32_GPT_USE_TIM11 FALSE
#define STM32_GPT_USE_TIM12 FALSE
#define STM32_GPT_USE_TIM13 FALSE
#define STM32_GPT_USE_TIM14 FALSE
#define STM32_GPT_TIM1_IRQ_PRIORITY 7
#define STM32_GPT_TIM2_IRQ_PRIORITY 7
#define STM32_GPT_TIM3_IRQ_PRIORITY 7
#define STM32_GPT_TIM4_IRQ_PRIORITY 7
#define STM32_GPT_TIM5_IRQ_PRIORITY 7
#define STM32_GPT_TIM6_IRQ_PRIORITY 7
#define STM32_GPT_TIM7_IRQ_PRIORITY 7
#define STM32_GPT_TIM8_IRQ_PRIORITY 7
#define STM32_GPT_TIM9_IRQ_PRIORITY 7
#define STM32_GPT_TIM11_IRQ_PRIORITY 7
#define STM32_GPT_TIM12_IRQ_PRIORITY 7
#define STM32_GPT_TIM14_IRQ_PRIORITY 7
/*
* I2C driver system settings.
@@ -199,13 +211,11 @@
#define STM32_ICU_USE_TIM5 FALSE
#define STM32_ICU_USE_TIM8 FALSE
#define STM32_ICU_USE_TIM9 FALSE
#define STM32_ICU_TIM1_IRQ_PRIORITY 7
#define STM32_ICU_TIM2_IRQ_PRIORITY 7
#define STM32_ICU_TIM3_IRQ_PRIORITY 7
#define STM32_ICU_TIM4_IRQ_PRIORITY 7
#define STM32_ICU_TIM5_IRQ_PRIORITY 7
#define STM32_ICU_TIM8_IRQ_PRIORITY 7
#define STM32_ICU_TIM9_IRQ_PRIORITY 7
#define STM32_ICU_USE_TIM10 FALSE
#define STM32_ICU_USE_TIM11 FALSE
#define STM32_ICU_USE_TIM12 FALSE
#define STM32_ICU_USE_TIM13 FALSE
#define STM32_ICU_USE_TIM14 FALSE
/*
* MAC driver system settings.
@@ -221,7 +231,6 @@
/*
* PWM driver system settings.
*/
#define STM32_PWM_USE_ADVANCED FALSE
#define STM32_PWM_USE_TIM1 FALSE
#define STM32_PWM_USE_TIM2 FALSE
#define STM32_PWM_USE_TIM3 FALSE
@@ -229,13 +238,11 @@
#define STM32_PWM_USE_TIM5 FALSE
#define STM32_PWM_USE_TIM8 FALSE
#define STM32_PWM_USE_TIM9 FALSE
#define STM32_PWM_TIM1_IRQ_PRIORITY 7
#define STM32_PWM_TIM2_IRQ_PRIORITY 7
#define STM32_PWM_TIM3_IRQ_PRIORITY 7
#define STM32_PWM_TIM4_IRQ_PRIORITY 7
#define STM32_PWM_TIM5_IRQ_PRIORITY 7
#define STM32_PWM_TIM8_IRQ_PRIORITY 7
#define STM32_PWM_TIM9_IRQ_PRIORITY 7
#define STM32_PWM_USE_TIM10 FALSE
#define STM32_PWM_USE_TIM11 FALSE
#define STM32_PWM_USE_TIM12 FALSE
#define STM32_PWM_USE_TIM13 FALSE
#define STM32_PWM_USE_TIM14 FALSE
/*
* RTC driver system settings.
@@ -265,12 +272,6 @@
#define STM32_SERIAL_USE_UART4 FALSE
#define STM32_SERIAL_USE_UART5 FALSE
#define STM32_SERIAL_USE_USART6 FALSE
#define STM32_SERIAL_USART1_PRIORITY 12
#define STM32_SERIAL_USART2_PRIORITY 12
#define STM32_SERIAL_USART3_PRIORITY 12
#define STM32_SERIAL_UART4_PRIORITY 12
#define STM32_SERIAL_UART5_PRIORITY 12
#define STM32_SERIAL_USART6_PRIORITY 12
/*
* SPI driver system settings.
@@ -319,12 +320,6 @@
#define STM32_UART_UART5_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
#define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
#define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
#define STM32_UART_USART1_IRQ_PRIORITY 12
#define STM32_UART_USART2_IRQ_PRIORITY 12
#define STM32_UART_USART3_IRQ_PRIORITY 12
#define STM32_UART_UART4_IRQ_PRIORITY 12
#define STM32_UART_UART5_IRQ_PRIORITY 12
#define STM32_UART_USART6_IRQ_PRIORITY 12
#define STM32_UART_USART1_DMA_PRIORITY 0
#define STM32_UART_USART2_DMA_PRIORITY 0
#define STM32_UART_USART3_DMA_PRIORITY 0

9
platforms/chibios/boards/GENERIC_STM32_F411XE/board/board.mk Normal file
View File

@@ -0,0 +1,9 @@
# List of all the board related files.
BOARDSRC = $(CHIBIOS)/os/hal/boards/ST_NUCLEO64_F411RE/board.c
# Required include directories
BOARDINC = $(CHIBIOS)/os/hal/boards/ST_NUCLEO64_F411RE
# Shared variables
ALLCSRC += $(BOARDSRC)
ALLINC += $(BOARDINC)

20
platforms/chibios/boards/GENERIC_STM32_F411XE/configs/board.h Normal file
View File

@@ -0,0 +1,20 @@
/* Copyright 2020 Nick Brassel (tzarc)
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <https://www.gnu.org/licenses/>.
*/
#pragma once
#include_next "board.h"
#undef STM32_HSE_BYPASS

22
platforms/chibios/boards/GENERIC_STM32_F411XE/configs/config.h Normal file
View File

@@ -0,0 +1,22 @@
/* Copyright 2020 Nick Brassel (tzarc)
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <https://www.gnu.org/licenses/>.
*/
#pragma once
#define BOARD_OTG_NOVBUSSENS 1
#ifndef EARLY_INIT_PERFORM_BOOTLOADER_JUMP
# define EARLY_INIT_PERFORM_BOOTLOADER_JUMP TRUE
#endif

252
platforms/chibios/boards/GENERIC_STM32_F411XE/configs/mcuconf.h Normal file
View File

@@ -0,0 +1,252 @@
/*
ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
#ifndef MCUCONF_H
#define MCUCONF_H
/*
* STM32F4xx drivers configuration.
* The following settings override the default settings present in
* the various device driver implementation headers.
* Note that the settings for each driver only have effect if the whole
* driver is enabled in halconf.h.
*
* IRQ priorities:
* 15...0 Lowest...Highest.
*
* DMA priorities:
* 0...3 Lowest...Highest.
*/
#define STM32F4xx_MCUCONF
#define STM32F411_MCUCONF
/*
* HAL driver system settings.
*/
#define STM32_NO_INIT FALSE
#define STM32_PVD_ENABLE FALSE
#define STM32_PLS STM32_PLS_LEV0
#define STM32_BKPRAM_ENABLE FALSE
#define STM32_HSI_ENABLED TRUE
#define STM32_LSI_ENABLED TRUE
#define STM32_HSE_ENABLED TRUE
#define STM32_LSE_ENABLED FALSE
#define STM32_CLOCK48_REQUIRED TRUE
#define STM32_SW STM32_SW_PLL
#define STM32_PLLSRC STM32_PLLSRC_HSE
#define STM32_PLLM_VALUE 4
#define STM32_PLLN_VALUE 96
#define STM32_PLLP_VALUE 2
#define STM32_PLLQ_VALUE 4
#define STM32_HPRE STM32_HPRE_DIV1
#define STM32_PPRE1 STM32_PPRE1_DIV2
#define STM32_PPRE2 STM32_PPRE2_DIV1
#define STM32_RTCSEL STM32_RTCSEL_LSI
#define STM32_RTCPRE_VALUE 8
#define STM32_MCO1SEL STM32_MCO1SEL_HSI
#define STM32_MCO1PRE STM32_MCO1PRE_DIV1
#define STM32_MCO2SEL STM32_MCO2SEL_SYSCLK
#define STM32_MCO2PRE STM32_MCO2PRE_DIV5
#define STM32_I2SSRC STM32_I2SSRC_CKIN
#define STM32_PLLI2SN_VALUE 192
#define STM32_PLLI2SR_VALUE 5
/*
* IRQ system settings.
*/
#define STM32_IRQ_EXTI0_PRIORITY 6
#define STM32_IRQ_EXTI1_PRIORITY 6
#define STM32_IRQ_EXTI2_PRIORITY 6
#define STM32_IRQ_EXTI3_PRIORITY 6
#define STM32_IRQ_EXTI4_PRIORITY 6
#define STM32_IRQ_EXTI5_9_PRIORITY 6
#define STM32_IRQ_EXTI10_15_PRIORITY 6
#define STM32_IRQ_EXTI16_PRIORITY 6
#define STM32_IRQ_EXTI17_PRIORITY 15
#define STM32_IRQ_EXTI18_PRIORITY 6
#define STM32_IRQ_EXTI19_PRIORITY 6
#define STM32_IRQ_EXTI20_PRIORITY 6
#define STM32_IRQ_EXTI21_PRIORITY 15
#define STM32_IRQ_EXTI22_PRIORITY 15
#define STM32_IRQ_TIM1_BRK_TIM9_PRIORITY 7
#define STM32_IRQ_TIM1_UP_TIM10_PRIORITY 7
#define STM32_IRQ_TIM1_TRGCO_TIM11_PRIORITY 7
#define STM32_IRQ_TIM1_CC_PRIORITY 7
#define STM32_IRQ_TIM2_PRIORITY 7
#define STM32_IRQ_TIM3_PRIORITY 7
#define STM32_IRQ_TIM4_PRIORITY 7
#define STM32_IRQ_TIM5_PRIORITY 7
#define STM32_IRQ_USART1_PRIORITY 12
#define STM32_IRQ_USART2_PRIORITY 12
#define STM32_IRQ_USART6_PRIORITY 12
/*
* ADC driver system settings.
*/
#define STM32_ADC_ADCPRE ADC_CCR_ADCPRE_DIV4
#define STM32_ADC_USE_ADC1 FALSE
#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(2, 4)
#define STM32_ADC_ADC1_DMA_PRIORITY 2
#define STM32_ADC_IRQ_PRIORITY 6
#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 6
/*
* GPT driver system settings.
*/
#define STM32_GPT_USE_TIM1 FALSE
#define STM32_GPT_USE_TIM2 FALSE
#define STM32_GPT_USE_TIM3 FALSE
#define STM32_GPT_USE_TIM4 FALSE
#define STM32_GPT_USE_TIM5 FALSE
#define STM32_GPT_USE_TIM9 FALSE
#define STM32_GPT_USE_TIM10 FALSE
#define STM32_GPT_USE_TIM11 FALSE
/*
* I2C driver system settings.
*/
#define STM32_I2C_USE_I2C1 FALSE
#define STM32_I2C_USE_I2C2 FALSE
#define STM32_I2C_USE_I2C3 FALSE
#define STM32_I2C_BUSY_TIMEOUT 50
#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0)
#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
#define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
#define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
#define STM32_I2C_I2C1_IRQ_PRIORITY 5
#define STM32_I2C_I2C2_IRQ_PRIORITY 5
#define STM32_I2C_I2C3_IRQ_PRIORITY 5
#define STM32_I2C_I2C1_DMA_PRIORITY 3
#define STM32_I2C_I2C2_DMA_PRIORITY 3
#define STM32_I2C_I2C3_DMA_PRIORITY 3
#define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure")
/*
* I2S driver system settings.
*/
#define STM32_I2S_USE_SPI2 FALSE
#define STM32_I2S_USE_SPI3 FALSE
#define STM32_I2S_SPI2_IRQ_PRIORITY 10
#define STM32_I2S_SPI3_IRQ_PRIORITY 10
#define STM32_I2S_SPI2_DMA_PRIORITY 1
#define STM32_I2S_SPI3_DMA_PRIORITY 1
#define STM32_I2S_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
#define STM32_I2S_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
#define STM32_I2S_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0)
#define STM32_I2S_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
#define STM32_I2S_DMA_ERROR_HOOK(i2sp) osalSysHalt("DMA failure")
/*
* ICU driver system settings.
*/
#define STM32_ICU_USE_TIM1 FALSE
#define STM32_ICU_USE_TIM2 FALSE
#define STM32_ICU_USE_TIM3 FALSE
#define STM32_ICU_USE_TIM4 FALSE
#define STM32_ICU_USE_TIM5 FALSE
#define STM32_ICU_USE_TIM9 FALSE
#define STM32_ICU_USE_TIM10 FALSE
#define STM32_ICU_USE_TIM11 FALSE
/*
* PWM driver system settings.
*/
#define STM32_PWM_USE_TIM1 FALSE
#define STM32_PWM_USE_TIM2 FALSE
#define STM32_PWM_USE_TIM3 FALSE
#define STM32_PWM_USE_TIM4 FALSE
#define STM32_PWM_USE_TIM5 FALSE
#define STM32_PWM_USE_TIM9 FALSE
#define STM32_PWM_USE_TIM10 FALSE
#define STM32_PWM_USE_TIM11 FALSE
/*
* RTC driver system settings.
*/
#define STM32_RTC_PRESA_VALUE 32
#define STM32_RTC_PRESS_VALUE 1024
#define STM32_RTC_CR_INIT 0
#define STM32_RTC_TAMPCR_INIT 0
/*
* SERIAL driver system settings.
*/
#define STM32_SERIAL_USE_USART1 FALSE
#define STM32_SERIAL_USE_USART2 FALSE
#define STM32_SERIAL_USE_USART6 FALSE
/*
* SPI driver system settings.
*/
#define STM32_SPI_USE_SPI1 FALSE
#define STM32_SPI_USE_SPI2 FALSE
#define STM32_SPI_USE_SPI3 FALSE
#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0)
#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3)
#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0)
#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
#define STM32_SPI_SPI1_DMA_PRIORITY 1
#define STM32_SPI_SPI2_DMA_PRIORITY 1
#define STM32_SPI_SPI3_DMA_PRIORITY 1
#define STM32_SPI_SPI1_IRQ_PRIORITY 10
#define STM32_SPI_SPI2_IRQ_PRIORITY 10
#define STM32_SPI_SPI3_IRQ_PRIORITY 10
#define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure")
/*
* ST driver system settings.
*/
#define STM32_ST_IRQ_PRIORITY 8
#define STM32_ST_USE_TIMER 2
/*
* UART driver system settings.
*/
#define STM32_UART_USE_USART1 FALSE
#define STM32_UART_USE_USART2 FALSE
#define STM32_UART_USE_USART6 FALSE
#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5)
#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
#define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
#define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
#define STM32_UART_USART1_DMA_PRIORITY 0
#define STM32_UART_USART2_DMA_PRIORITY 0
#define STM32_UART_USART6_DMA_PRIORITY 0
#define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure")
/*
* USB driver system settings.
*/
#define STM32_USB_USE_OTG1 TRUE
#define STM32_USB_OTG1_IRQ_PRIORITY 14
#define STM32_USB_OTG1_RX_FIFO_SIZE 512
#define STM32_USB_HOST_WAKEUP_DURATION 2
/*
* WDG driver system settings.
*/
#define STM32_WDG_USE_IWDG FALSE
#endif /* MCUCONF_H */

20
platforms/chibios/boards/GENERIC_STM32_G431XB/configs/mcuconf.h
View File

@@ -1,5 +1,5 @@
/*
ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
@@ -39,6 +39,7 @@
* HAL driver system settings.
*/
#define STM32_NO_INIT FALSE
#define STM32_CLOCK_DYNAMIC FALSE
#define STM32_VOS STM32_VOS_RANGE1
#define STM32_PWR_BOOST TRUE
#define STM32_PWR_CR2 (PWR_CR2_PLS_LEV0)
@@ -227,7 +228,6 @@
/*
* PWM driver system settings.
*/
#define STM32_PWM_USE_ADVANCED FALSE
#define STM32_PWM_USE_TIM1 FALSE
#define STM32_PWM_USE_TIM2 FALSE
#define STM32_PWM_USE_TIM3 FALSE
@@ -240,6 +240,13 @@
/*
* RTC driver system settings.
*/
#define STM32_RTC_PRESA_VALUE 32
#define STM32_RTC_PRESS_VALUE 1024
#define STM32_RTC_CR_INIT 0
#define STM32_TAMP_CR1_INIT 0
#define STM32_TAMP_CR2_INIT 0
#define STM32_TAMP_FLTCR_INIT 0
#define STM32_TAMP_IER_INIT 0
/*
* SDC driver system settings.
@@ -254,6 +261,15 @@
#define STM32_SERIAL_USE_UART4 FALSE
#define STM32_SERIAL_USE_LPUART1 FALSE
/*
* SIO driver system settings.
*/
#define STM32_SIO_USE_USART1 FALSE
#define STM32_SIO_USE_USART2 FALSE
#define STM32_SIO_USE_USART3 FALSE
#define STM32_SIO_USE_UART4 FALSE
#define STM32_SIO_USE_LPUART1 FALSE
/*
* SPI driver system settings.
*/

22
platforms/chibios/boards/GENERIC_STM32_G474XE/configs/mcuconf.h
View File

@@ -1,5 +1,5 @@
/*
ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
@@ -41,6 +41,7 @@
* HAL driver system settings.
*/
#define STM32_NO_INIT FALSE
#define STM32_CLOCK_DYNAMIC FALSE
#define STM32_VOS STM32_VOS_RANGE1
#define STM32_PWR_BOOST TRUE
#define STM32_PWR_CR2 (PWR_CR2_PLS_LEV0)
@@ -274,7 +275,6 @@
/*
* PWM driver system settings.
*/
#define STM32_PWM_USE_ADVANCED FALSE
#define STM32_PWM_USE_TIM1 FALSE
#define STM32_PWM_USE_TIM2 FALSE
#define STM32_PWM_USE_TIM3 FALSE
@@ -289,6 +289,13 @@
/*
* RTC driver system settings.
*/
#define STM32_RTC_PRESA_VALUE 32
#define STM32_RTC_PRESS_VALUE 1024
#define STM32_RTC_CR_INIT 0
#define STM32_TAMP_CR1_INIT 0
#define STM32_TAMP_CR2_INIT 0
#define STM32_TAMP_FLTCR_INIT 0
#define STM32_TAMP_IER_INIT 0
/*
* SDC driver system settings.
@@ -304,6 +311,16 @@
#define STM32_SERIAL_USE_UART5 FALSE
#define STM32_SERIAL_USE_LPUART1 FALSE
/*
* SIO driver system settings.
*/
#define STM32_SIO_USE_USART1 FALSE
#define STM32_SIO_USE_USART2 FALSE
#define STM32_SIO_USE_USART3 FALSE
#define STM32_SIO_USE_UART4 FALSE
#define STM32_SIO_USE_UART5 FALSE
#define STM32_SIO_USE_LPUART1 FALSE
/*
* SPI driver system settings.
*/
@@ -383,5 +400,6 @@
*/
#define STM32_WSPI_USE_QUADSPI1 FALSE
#define STM32_WSPI_QUADSPI1_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
#define STM32_WSPI_QUADSPI1_PRESCALER_VALUE 1
#endif /* MCUCONF_H */

5
platforms/chibios/boards/GENERIC_STM32_L412XB/configs/board.h
View File

@@ -18,7 +18,4 @@
#include_next "board.h"
#undef STM32L432xx
// Pretend that we're an L443xx as the ChibiOS definitions for L4x2/L4x3 mistakenly don't enable GPIOH, I2C2, or SPI2.
// Until ChibiOS upstream is fixed, this should be kept at L443, as nothing in QMK currently utilises the crypto peripheral on the L443.
#define STM32L443xx
#define STM32L422xx

2
platforms/chibios/boards/GENERIC_STM32_L412XB/configs/config.h
View File

@@ -18,8 +18,6 @@
/* It is chip dependent, the correct number can be looked up by checking against ST's application note AN2606.
*/
#define PAL_STM32_OSPEED_HIGHEST PAL_STM32_OSPEED_HIGH
#ifndef EARLY_INIT_PERFORM_BOOTLOADER_JUMP
# define EARLY_INIT_PERFORM_BOOTLOADER_JUMP TRUE
#endif

60
platforms/chibios/boards/GENERIC_STM32_L412XB/configs/mcuconf.h
View File

@@ -1,5 +1,5 @@
/*
ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
@@ -32,12 +32,7 @@
#define MCUCONF_H
#define STM32L4xx_MCUCONF
#define STM32L412_MCUCONF
#define STM32L422_MCUCONF
#define STM32L432_MCUCONF
#define STM32L433_MCUCONF
#define STM32L442_MCUCONF
#define STM32L443_MCUCONF
/*
* HAL driver system settings.
@@ -52,16 +47,13 @@
#define STM32_HSE_ENABLED FALSE
#define STM32_LSE_ENABLED FALSE
#define STM32_MSIPLL_ENABLED FALSE
#define STM32_ADC_CLOCK_ENABLED TRUE
#define STM32_USB_CLOCK_ENABLED TRUE
#define STM32_SAI1_CLOCK_ENABLED TRUE
#define STM32_SAI2_CLOCK_ENABLED TRUE
#define STM32_MSIRANGE STM32_MSIRANGE_4M
#define STM32_MSISRANGE STM32_MSISRANGE_4M
#define STM32_SW STM32_SW_PLL
#define STM32_PLLSRC STM32_PLLSRC_HSI16
#define STM32_PLLM_VALUE 4
#define STM32_PLLN_VALUE 80
#define STM32_PLLPDIV_VALUE 0
#define STM32_PLLP_VALUE 7
#define STM32_PLLQ_VALUE 4
#define STM32_PLLR_VALUE 4
@@ -73,29 +65,22 @@
#define STM32_MCOPRE STM32_MCOPRE_DIV1
#define STM32_LSCOSEL STM32_LSCOSEL_NOCLOCK
#define STM32_PLLSAI1N_VALUE 72
#define STM32_PLLSAI1PDIV_VALUE 6
#define STM32_PLLSAI1P_VALUE 7
#define STM32_PLLSAI1Q_VALUE 6
#define STM32_PLLSAI1R_VALUE 6
#define STM32_PLLSAI2N_VALUE 72
#define STM32_PLLSAI2P_VALUE 7
#define STM32_PLLSAI2R_VALUE 6
/*
* Peripherals clock sources.
*/
#define STM32_USART1SEL STM32_USART1SEL_SYSCLK
#define STM32_USART2SEL STM32_USART2SEL_SYSCLK
#define STM32_USART3SEL STM32_USART3SEL_SYSCLK
#define STM32_UART4SEL STM32_UART4SEL_SYSCLK
#define STM32_UART5SEL STM32_UART5SEL_SYSCLK
#define STM32_LPUART1SEL STM32_LPUART1SEL_SYSCLK
#define STM32_I2C1SEL STM32_I2C1SEL_SYSCLK
#define STM32_I2C2SEL STM32_I2C2SEL_SYSCLK
#define STM32_I2C3SEL STM32_I2C3SEL_SYSCLK
#define STM32_LPTIM1SEL STM32_LPTIM1SEL_PCLK1
#define STM32_LPTIM2SEL STM32_LPTIM2SEL_PCLK1
#define STM32_SAI1SEL STM32_SAI1SEL_OFF
#define STM32_SAI2SEL STM32_SAI2SEL_OFF
#define STM32_CLK48SEL STM32_CLK48SEL_HSI48
#define STM32_ADCSEL STM32_ADCSEL_SYSCLK
#define STM32_SWPMI1SEL STM32_SWPMI1SEL_PCLK1
@@ -127,7 +112,6 @@
#define STM32_IRQ_USART1_PRIORITY 12
#define STM32_IRQ_USART2_PRIORITY 12
#define STM32_IRQ_USART3_PRIORITY 12
#define STM32_IRQ_LPUART1_PRIORITY 12
/*
@@ -137,29 +121,15 @@
#define STM32_ADC_USE_ADC1 FALSE
#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(1, 1)
#define STM32_ADC_ADC1_DMA_PRIORITY 2
#define STM32_ADC_USE_ADC2 FALSE
#define STM32_ADC_ADC2_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
#define STM32_ADC_ADC2_DMA_PRIORITY 2
#define STM32_ADC_ADC12_IRQ_PRIORITY 5
#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 5
#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 5
#define STM32_ADC_ADC123_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV1
#define STM32_ADC_ADC123_PRESC ADC_CCR_PRESC_DIV2
/*
* CAN driver system settings.
*/
#define STM32_CAN_USE_CAN1 FALSE
#define STM32_CAN_CAN1_IRQ_PRIORITY 11
/*
* DAC driver system settings.
*/
#define STM32_DAC_DUAL_MODE FALSE
#define STM32_DAC_USE_DAC1_CH1 FALSE
#define STM32_DAC_USE_DAC1_CH2 FALSE
#define STM32_DAC_DAC1_CH1_IRQ_PRIORITY 10
#define STM32_DAC_DAC1_CH2_IRQ_PRIORITY 10
#define STM32_DAC_DAC1_CH1_DMA_PRIORITY 2
#define STM32_DAC_DAC1_CH2_DMA_PRIORITY 2
#define STM32_DAC_DAC1_CH1_DMA_STREAM STM32_DMA_STREAM_ID(2, 4)
#define STM32_DAC_DAC1_CH2_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
/*
* GPT driver system settings.
@@ -198,7 +168,6 @@
/*
* PWM driver system settings.
*/
#define STM32_PWM_USE_ADVANCED FALSE
#define STM32_PWM_USE_TIM1 FALSE
#define STM32_PWM_USE_TIM2 FALSE
#define STM32_PWM_USE_TIM15 FALSE
@@ -218,23 +187,22 @@
#define STM32_SERIAL_USE_USART1 FALSE
#define STM32_SERIAL_USE_USART2 FALSE
#define STM32_SERIAL_USE_LPUART1 FALSE
#define STM32_SERIAL_USART1_PRIORITY 12
#define STM32_SERIAL_USART2_PRIORITY 12
#define STM32_SERIAL_LPUART1_PRIORITY 12
/*
* SIO driver system settings.
*/
#define STM32_SIO_USE_USART1 FALSE
#define STM32_SIO_USE_USART2 FALSE
#define STM32_SIO_USE_LPUART1 FALSE
/*
* SPI driver system settings.
*/
#define STM32_SPI_USE_SPI1 FALSE
#define STM32_SPI_USE_SPI3 FALSE
#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3)
#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 4)
#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 1)
#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
#define STM32_SPI_SPI1_DMA_PRIORITY 1
#define STM32_SPI_SPI3_DMA_PRIORITY 1
#define STM32_SPI_SPI1_IRQ_PRIORITY 10
#define STM32_SPI_SPI3_IRQ_PRIORITY 10
#define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure")
/*

3
platforms/chibios/boards/GENERIC_STM32_L432XC/configs/config.h
View File

@@ -2,9 +2,6 @@
// SPDX-License-Identifier: GPL-2.0-or-later
#pragma once
// Fixup equivalent usages within QMK as the base board definitions only go up to high
#define PAL_STM32_OSPEED_HIGHEST PAL_STM32_OSPEED_HIGH
#ifndef EARLY_INIT_PERFORM_BOOTLOADER_JUMP
# define EARLY_INIT_PERFORM_BOOTLOADER_JUMP TRUE
#endif

14
platforms/chibios/boards/GENERIC_STM32_L432XC/configs/mcuconf.h
View File

@@ -1,5 +1,5 @@
/*
ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
@@ -33,7 +33,6 @@
#define STM32L4xx_MCUCONF
#define STM32L432_MCUCONF
#define STM32L433_MCUCONF
/*
* HAL driver system settings.
@@ -183,7 +182,6 @@
/*
* PWM driver system settings.
*/
#define STM32_PWM_USE_ADVANCED FALSE
#define STM32_PWM_USE_TIM1 FALSE
#define STM32_PWM_USE_TIM2 FALSE
#define STM32_PWM_USE_TIM15 FALSE
@@ -203,9 +201,13 @@
#define STM32_SERIAL_USE_USART1 FALSE
#define STM32_SERIAL_USE_USART2 FALSE
#define STM32_SERIAL_USE_LPUART1 FALSE
#define STM32_SERIAL_USART1_PRIORITY 12
#define STM32_SERIAL_USART2_PRIORITY 12
#define STM32_SERIAL_LPUART1_PRIORITY 12
/*
* SIO driver system settings.
*/
#define STM32_SIO_USE_USART1 FALSE
#define STM32_SIO_USE_USART2 FALSE
#define STM32_SIO_USE_LPUART1 FALSE
/*
* SPI driver system settings.

2
platforms/chibios/boards/GENERIC_STM32_L433XC/configs/config.h
View File

@@ -18,8 +18,6 @@
/* It is chip dependent, the correct number can be looked up by checking against ST's application note AN2606.
*/
#define PAL_STM32_OSPEED_HIGHEST PAL_STM32_OSPEED_HIGH
#ifndef EARLY_INIT_PERFORM_BOOTLOADER_JUMP
# define EARLY_INIT_PERFORM_BOOTLOADER_JUMP TRUE
#endif

5
platforms/chibios/boards/GENERIC_WB32_F3G71XX/board/board.h
View File

@@ -34,7 +34,10 @@
/*
* Board identifier.
*/
#define WB32F3G71x9
#if !(defined(WB32F3G71x9) || defined(WB32F3G71xB) || defined(WB32F3G71xC))
#define WB32F3G71x9
#endif
#if !defined(WB32F3G71xx)
#define WB32F3G71xx
#endif

82
platforms/chibios/boards/GENERIC_WB32_FQ95XX/board/board.c Normal file
View File

@@ -0,0 +1,82 @@
/*
Copyright (C) 2022 Westberry Technology (ChangZhou) Corp., Ltd
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/*
* This file has been automatically generated using ChibiStudio board
* generator plugin. Do not edit manually.
*/
#include "hal.h"
/*===========================================================================*/
/* Driver local definitions. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver exported variables. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver local variables and types. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver local functions. */
/*===========================================================================*/
static void wb32_gpio_init(void) {
#if WB32_HAS_GPIOA
rccEnableAPB1(RCC_APB1ENR_GPIOAEN);
#endif
#if WB32_HAS_GPIOB
rccEnableAPB1(RCC_APB1ENR_GPIOBEN);
#endif
#if WB32_HAS_GPIOC
rccEnableAPB1(RCC_APB1ENR_GPIOCEN);
#endif
#if WB32_HAS_GPIOD
rccEnableAPB1(RCC_APB1ENR_GPIODEN);
#endif
}
/*===========================================================================*/
/* Driver interrupt handlers. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver exported functions. */
/*===========================================================================*/
/*
* Early initialization code.
* This initialization must be performed just after stack setup and before
* any other initialization.
*/
void __early_init(void) {
wb32_clock_init();
wb32_gpio_init();
}
/**
* @brief Board-specific initialization code.
* @note You can add your board-specific code here.
*/
void boardInit(void) {
}

59
platforms/chibios/boards/GENERIC_WB32_FQ95XX/board/board.h Normal file
View File

@@ -0,0 +1,59 @@
#pragma once
/*
Copyright (C) 2022 Westberry Technology (ChangZhou) Corp., Ltd
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/*
* This file has been automatically generated using ChibiStudio board
* generator plugin. Do not edit manually.
*/
#ifndef BOARD_H
#define BOARD_H
/*===========================================================================*/
/* Driver constants. */
/*===========================================================================*/
/*
* Setup board.
*/
/*
* Board identifier.
*/
#if !(defined(WB32FQ95x9) || defined(WB32FQ95xB) || defined(WB32FQ95xC))
#define WB32FQ95xB
#endif
#if !defined(WB32FQ95xx)
#define WB32FQ95xx
#endif
/*===========================================================================*/
/* External declarations. */
/*===========================================================================*/
#if !defined(_FROM_ASM_)
#ifdef __cplusplus
extern "C" {
#endif
void boardInit(void);
#ifdef __cplusplus
}
#endif
#endif /* _FROM_ASM_ */
#endif /* BOARD_H */

9
platforms/chibios/boards/GENERIC_WB32_FQ95XX/board/board.mk Normal file
View File

@@ -0,0 +1,9 @@
# List of all the board related files.
BOARDSRC = $(BOARD_PATH)/board/board.c
# Required include directories
BOARDINC = $(BOARD_PATH)/board
# Shared variables
ALLCSRC += $(BOARDSRC)
ALLINC += $(BOARDINC)

20
platforms/chibios/boards/GENERIC_WB32_FQ95XX/configs/config.h Normal file
View File

@@ -0,0 +1,20 @@
/* Copyright (C) 2022 Westberry Technology (ChangZhou) Corp., Ltd
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <https://www.gnu.org/licenses/>.
*/
#pragma once
#ifndef EARLY_INIT_PERFORM_BOOTLOADER_JUMP
# define EARLY_INIT_PERFORM_BOOTLOADER_JUMP TRUE
#endif

168
platforms/chibios/boards/GENERIC_WB32_FQ95XX/configs/mcuconf.h Normal file
View File

@@ -0,0 +1,168 @@
/*
Copyright (C) 2022 Westberry Technology (ChangZhou) Corp., Ltd
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
#ifndef MCUCONF_H
#define MCUCONF_H
#define WB32FQ95xx_MCUCONF TRUE
/*
* WB32FQ95 drivers configuration.
* The following settings override the default settings present in
* the various device driver implementation headers.
* Note that the settings for each driver only have effect if the whole
* driver is enabled in halconf.h.
*
* IRQ priorities:
* 15...0 Lowest...Highest.
*
*/
/**
* @name Internal clock sources
* @{
*/
#define WB32_HSECLK 12000000
#define WB32_LSECLK 32768
/*
* HAL driver system settings.
*/
#define WB32_NO_INIT FALSE
#define WB32_MHSI_ENABLED TRUE
#define WB32_FHSI_ENABLED FALSE
#define WB32_LSI_ENABLED FALSE
#define WB32_HSE_ENABLED TRUE
#define WB32_LSE_ENABLED FALSE
#define WB32_PLL_ENABLED TRUE
#define WB32_MAINCLKSRC WB32_MAINCLKSRC_PLL
#define WB32_PLLSRC WB32_PLLSRC_HSE
#define WB32_PLLDIV_VALUE 2
#define WB32_PLLMUL_VALUE 12 //The allowed range is 12,16,20,24.
#define WB32_HPRE 1
#define WB32_PPRE1 1
#define WB32_PPRE2 1
#define WB32_USBPRE WB32_USBPRE_DIV1P5
/*
* EXTI driver system settings.
*/
#define WB32_IRQ_EXTI0_PRIORITY 6
#define WB32_IRQ_EXTI1_PRIORITY 6
#define WB32_IRQ_EXTI2_PRIORITY 6
#define WB32_IRQ_EXTI3_PRIORITY 6
#define WB32_IRQ_EXTI4_PRIORITY 6
#define WB32_IRQ_EXTI5_9_PRIORITY 6
#define WB32_IRQ_EXTI10_15_PRIORITY 6
#define WB32_IRQ_EXTI16_PRIORITY 6
#define WB32_IRQ_EXTI17_PRIORITY 6
#define WB32_IRQ_EXTI18_PRIORITY 6
#define WB32_IRQ_EXTI19_PRIORITY 6
/*
* GPT driver system settings.
*/
#define WB32_TIM_MAX_CHANNELS 4
#define WB32_GPT_USE_TIM1 FALSE
#define WB32_GPT_USE_TIM2 FALSE
#define WB32_GPT_USE_TIM3 FALSE
#define WB32_GPT_USE_TIM4 FALSE
#define WB32_GPT_TIM1_IRQ_PRIORITY 7
#define WB32_GPT_TIM2_IRQ_PRIORITY 7
#define WB32_GPT_TIM3_IRQ_PRIORITY 7
#define WB32_GPT_TIM4_IRQ_PRIORITY 7
/*
* ICU driver system settings.
*/
#define WB32_ICU_USE_TIM1 FALSE
#define WB32_ICU_USE_TIM2 FALSE
#define WB32_ICU_USE_TIM3 FALSE
#define WB32_ICU_USE_TIM4 FALSE
#define WB32_ICU_TIM1_IRQ_PRIORITY 7
#define WB32_ICU_TIM2_IRQ_PRIORITY 7
#define WB32_ICU_TIM3_IRQ_PRIORITY 7
#define WB32_ICU_TIM4_IRQ_PRIORITY 7
/*
* PWM driver system settings.
*/
#define WB32_PWM_USE_ADVANCED FALSE
#define WB32_PWM_USE_TIM1 FALSE
#define WB32_PWM_USE_TIM2 FALSE
#define WB32_PWM_USE_TIM3 FALSE
#define WB32_PWM_USE_TIM4 FALSE
#define WB32_PWM_TIM1_IRQ_PRIORITY 7
#define WB32_PWM_TIM2_IRQ_PRIORITY 7
#define WB32_PWM_TIM3_IRQ_PRIORITY 7
#define WB32_PWM_TIM4_IRQ_PRIORITY 7
/*
* I2C driver system settings.
*/
#define WB32_I2C_USE_I2C1 FALSE
#define WB32_I2C_USE_I2C2 FALSE
#define WB32_I2C_BUSY_TIMEOUT 50
#define WB32_I2C_I2C1_IRQ_PRIORITY 5
#define WB32_I2C_I2C2_IRQ_PRIORITY 5
/*
* SERIAL driver system settings.
*/
#define WB32_SERIAL_USE_UART1 FALSE
#define WB32_SERIAL_USE_UART2 FALSE
#define WB32_SERIAL_USE_UART3 FALSE
#define WB32_SERIAL_USART1_PRIORITY 12
#define WB32_SERIAL_USART2_PRIORITY 12
#define WB32_SERIAL_USART3_PRIORITY 12
/*
* SPI driver system settings.
*/
#define WB32_SPI_USE_QSPI FALSE
#define WB32_SPI_USE_SPIM2 FALSE
#define WB32_SPI_USE_SPIS1 FALSE
#define WB32_SPI_USE_SPIS2 FALSE
#define WB32_SPI_QSPI_IRQ_PRIORITY 10
#define WB32_SPI_SPIM2_IRQ_PRIORITY 10
#define WB32_SPI_SPIS1_IRQ_PRIORITY 10
#define WB32_SPI_SPIS2_IRQ_PRIORITY 10
/*
* ST driver system settings.
*/
#define WB32_ST_IRQ_PRIORITY 8
#define WB32_ST_USE_TIMER 2
/*
* UART driver system settings.
*/
#define WB32_UART_USE_UART1 FALSE
#define WB32_UART_USE_UART2 FALSE
#define WB32_UART_USE_UART3 FALSE
#define WB32_UART_UART1_IRQ_PRIORITY 12
#define WB32_UART_UART2_IRQ_PRIORITY 12
#define WB32_UART_UART3_IRQ_PRIORITY 12
/*
* USB driver system settings.
*/
#define WB32_USB_USE_USB1 TRUE
#define WB32_USB_USB1_IRQ_PRIORITY 13
#define WB32_USB_HOST_WAKEUP_DURATION 10
#endif /* MCUCONF_H */

69
platforms/chibios/boards/QMK_PROTON_C/configs/chconf.h
View File

@@ -1,5 +1,5 @@
/*
ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
@@ -29,7 +29,27 @@
#define CHCONF_H
#define _CHIBIOS_RT_CONF_
#define _CHIBIOS_RT_CONF_VER_6_1_
#define _CHIBIOS_RT_CONF_VER_7_0_
/*===========================================================================*/
/**
* @name System settings
* @{
*/
/*===========================================================================*/
/**
* @brief Handling of instances.
* @note If enabled then threads assigned to various instances can
* interact each other using the same synchronization objects.
* If disabled then each OS instance is a separate world, no
* direct interactions are handled by the OS.
*/
#if !defined(CH_CFG_SMP_MODE)
#define CH_CFG_SMP_MODE FALSE
#endif
/** @} */
/*===========================================================================*/
/**
@@ -160,6 +180,16 @@
#define CH_CFG_USE_TM TRUE
#endif
/**
* @brief Time Stamps APIs.
* @details If enabled then the time stamps APIs are included in the kernel.
*
* @note The default is @p TRUE.
*/
#if !defined(CH_CFG_USE_TIMESTAMP)
#define CH_CFG_USE_TIMESTAMP TRUE
#endif
/**
* @brief Threads registry APIs.
* @details If enabled then the registry APIs are included in the kernel.
@@ -631,7 +661,7 @@
* @details User fields added to the end of the @p ch_system_t structure.
*/
#define CH_CFG_SYSTEM_EXTRA_FIELDS \
/* Add threads custom fields here.*/
/* Add system custom fields here.*/
/**
* @brief System initialization hook.
@@ -639,7 +669,23 @@
* just before interrupts are enabled globally.
*/
#define CH_CFG_SYSTEM_INIT_HOOK() { \
/* Add threads initialization code here.*/ \
/* Add system initialization code here.*/ \
}
/**
* @brief OS instance structure extension.
* @details User fields added to the end of the @p os_instance_t structure.
*/
#define CH_CFG_OS_INSTANCE_EXTRA_FIELDS \
/* Add OS instance custom fields here.*/
/**
* @brief OS instance initialization hook.
*
* @param[in] oip pointer to the @p os_instance_t structure
*/
#define CH_CFG_OS_INSTANCE_INIT_HOOK(oip) { \
/* Add OS instance initialization code here.*/ \
}
/**
@@ -655,6 +701,8 @@
*
* @note It is invoked from within @p _thread_init() and implicitly from all
* the threads creation APIs.
*
* @param[in] tp pointer to the @p thread_t structure
*/
#define CH_CFG_THREAD_INIT_HOOK(tp) { \
/* Add threads initialization code here.*/ \
@@ -663,6 +711,8 @@
/**
* @brief Threads finalization hook.
* @details User finalization code added to the @p chThdExit() API.
*
* @param[in] tp pointer to the @p thread_t structure
*/
#define CH_CFG_THREAD_EXIT_HOOK(tp) { \
/* Add threads finalization code here.*/ \
@@ -671,6 +721,9 @@
/**
* @brief Context switch hook.
* @details This hook is invoked just before switching between threads.
*
* @param[in] ntp thread being switched in
* @param[in] otp thread being switched out
*/
#define CH_CFG_CONTEXT_SWITCH_HOOK(ntp, otp) { \
/* Context switch code here.*/ \
@@ -745,6 +798,14 @@
/* Trace code here.*/ \
}
/**
* @brief Runtime Faults Collection Unit hook.
* @details This hook is invoked each time new faults are collected and stored.
*/
#define CH_CFG_RUNTIME_FAULTS_HOOK(mask) { \
/* Faults handling code here.*/ \
}
/** @} */
/*===========================================================================*/

31
platforms/chibios/boards/QMK_PROTON_C/configs/halconf.h
View File

@@ -1,5 +1,5 @@
/*
ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
@@ -29,7 +29,7 @@
#define HALCONF_H
#define _CHIBIOS_HAL_CONF_
#define _CHIBIOS_HAL_CONF_VER_7_1_
#define _CHIBIOS_HAL_CONF_VER_8_0_
#include <mcuconf.h>
@@ -415,6 +415,26 @@
#define SERIAL_BUFFERS_SIZE 128
#endif
/*===========================================================================*/
/* SIO driver related settings. */
/*===========================================================================*/
/**
* @brief Default bit rate.
* @details Configuration parameter, this is the baud rate selected for the
* default configuration.
*/
#if !defined(SIO_DEFAULT_BITRATE) || defined(__DOXYGEN__)
#define SIO_DEFAULT_BITRATE 38400
#endif
/**
* @brief Support for thread synchronization API.
*/
#if !defined(SIO_USE_SYNCHRONIZATION) || defined(__DOXYGEN__)
#define SIO_USE_SYNCHRONIZATION TRUE
#endif
/*===========================================================================*/
/* SERIAL_USB driver related setting. */
/*===========================================================================*/
@@ -451,11 +471,10 @@
#endif
/**
* @brief Enables circular transfers APIs.
* @note Disabling this option saves both code and data space.
* @brief Inserts an assertion on function errors before returning.
*/
#if !defined(SPI_USE_CIRCULAR) || defined(__DOXYGEN__)
#define SPI_USE_CIRCULAR FALSE
#if !defined(SPI_USE_ASSERT_ON_ERROR) || defined(__DOXYGEN__)
#define SPI_USE_ASSERT_ON_ERROR TRUE
#endif
/**

3
platforms/chibios/boards/QMK_PROTON_C/configs/mcuconf.h
View File

@@ -1,5 +1,5 @@
/*
ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
@@ -186,7 +186,6 @@
/*
* PWM driver system settings.
*/
#define STM32_PWM_USE_ADVANCED FALSE
#define STM32_PWM_USE_TIM1 FALSE
#define STM32_PWM_USE_TIM2 FALSE
#define STM32_PWM_USE_TIM3 TRUE

3
platforms/chibios/boards/STM32_F103_STM32DUINO/board/board.c
View File

@@ -16,9 +16,6 @@
#include <hal.h>
// Value to place in RTC backup register 10 for persistent bootloader mode
#define RTC_BOOTLOADER_FLAG 0x424C
/**
* @brief PAL setup.
* @details Digital I/O ports static configuration as defined in @p board.h.

8
platforms/chibios/boards/STM32_F103_STM32DUINO/configs/chconf.h Normal file
View File

@@ -0,0 +1,8 @@
// Copyright 2022 QMK
// SPDX-License-Identifier: GPL-2.0-or-later
#pragma once
#define CH_CFG_ST_TIMEDELTA 0
#include_next <chconf.h>

9
platforms/chibios/boards/STM32_F103_STM32DUINO/configs/config.h Normal file
View File

@@ -0,0 +1,9 @@
// Copyright 2022 Nick Brassel (@tzarc)
// SPDX-License-Identifier: GPL-2.0-or-later
#pragma once
// Value to place in RTC backup register 10 for persistent bootloader mode
#define RTC_BOOTLOADER_FLAG 0x424C
// Value to place in RTC backup register 10 for instant reboot mode
#define RTC_BOOTLOADER_JUST_UPLOADED 0x424D

69
platforms/chibios/boards/common/configs/chconf.h
View File

@@ -1,5 +1,5 @@
/*
ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
@@ -29,7 +29,27 @@
#define CHCONF_H
#define _CHIBIOS_RT_CONF_
#define _CHIBIOS_RT_CONF_VER_6_1_
#define _CHIBIOS_RT_CONF_VER_7_0_
/*===========================================================================*/
/**
* @name System settings
* @{
*/
/*===========================================================================*/
/**
* @brief Handling of instances.
* @note If enabled then threads assigned to various instances can
* interact each other using the same synchronization objects.
* If disabled then each OS instance is a separate world, no
* direct interactions are handled by the OS.
*/
#if !defined(CH_CFG_SMP_MODE)
#define CH_CFG_SMP_MODE FALSE
#endif
/** @} */
/*===========================================================================*/
/**
@@ -160,6 +180,16 @@
#define CH_CFG_USE_TM FALSE
#endif
/**
* @brief Time Stamps APIs.
* @details If enabled then the time stamps APIs are included in the kernel.
*
* @note The default is @p TRUE.
*/
#if !defined(CH_CFG_USE_TIMESTAMP)
#define CH_CFG_USE_TIMESTAMP TRUE
#endif
/**
* @brief Threads registry APIs.
* @details If enabled then the registry APIs are included in the kernel.
@@ -631,7 +661,7 @@
* @details User fields added to the end of the @p ch_system_t structure.
*/
#define CH_CFG_SYSTEM_EXTRA_FIELDS \
/* Add threads custom fields here.*/
/* Add system custom fields here.*/
/**
* @brief System initialization hook.
@@ -639,7 +669,23 @@
* just before interrupts are enabled globally.
*/
#define CH_CFG_SYSTEM_INIT_HOOK() { \
/* Add threads initialization code here.*/ \
/* Add system initialization code here.*/ \
}
/**
* @brief OS instance structure extension.
* @details User fields added to the end of the @p os_instance_t structure.
*/
#define CH_CFG_OS_INSTANCE_EXTRA_FIELDS \
/* Add OS instance custom fields here.*/
/**
* @brief OS instance initialization hook.
*
* @param[in] oip pointer to the @p os_instance_t structure
*/
#define CH_CFG_OS_INSTANCE_INIT_HOOK(oip) { \
/* Add OS instance initialization code here.*/ \
}
/**
@@ -655,6 +701,8 @@
*
* @note It is invoked from within @p _thread_init() and implicitly from all
* the threads creation APIs.
*
* @param[in] tp pointer to the @p thread_t structure
*/
#define CH_CFG_THREAD_INIT_HOOK(tp) { \
/* Add threads initialization code here.*/ \
@@ -663,6 +711,8 @@
/**
* @brief Threads finalization hook.
* @details User finalization code added to the @p chThdExit() API.
*
* @param[in] tp pointer to the @p thread_t structure
*/
#define CH_CFG_THREAD_EXIT_HOOK(tp) { \
/* Add threads finalization code here.*/ \
@@ -671,6 +721,9 @@
/**
* @brief Context switch hook.
* @details This hook is invoked just before switching between threads.
*
* @param[in] ntp thread being switched in
* @param[in] otp thread being switched out
*/
#define CH_CFG_CONTEXT_SWITCH_HOOK(ntp, otp) { \
/* Context switch code here.*/ \
@@ -745,6 +798,14 @@
/* Trace code here.*/ \
}
/**
* @brief Runtime Faults Collection Unit hook.
* @details This hook is invoked each time new faults are collected and stored.
*/
#define CH_CFG_RUNTIME_FAULTS_HOOK(mask) { \
/* Faults handling code here.*/ \
}
/** @} */
/*===========================================================================*/

31
platforms/chibios/boards/common/configs/halconf.h
View File

@@ -1,5 +1,5 @@
/*
ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
@@ -29,7 +29,7 @@
#define HALCONF_H
#define _CHIBIOS_HAL_CONF_
#define _CHIBIOS_HAL_CONF_VER_7_1_
#define _CHIBIOS_HAL_CONF_VER_8_0_
#include <mcuconf.h>
@@ -415,6 +415,26 @@
#define SERIAL_BUFFERS_SIZE 128
#endif
/*===========================================================================*/
/* SIO driver related settings. */
/*===========================================================================*/
/**
* @brief Default bit rate.
* @details Configuration parameter, this is the baud rate selected for the
* default configuration.
*/
#if !defined(SIO_DEFAULT_BITRATE) || defined(__DOXYGEN__)
#define SIO_DEFAULT_BITRATE 38400
#endif
/**
* @brief Support for thread synchronization API.
*/
#if !defined(SIO_USE_SYNCHRONIZATION) || defined(__DOXYGEN__)
#define SIO_USE_SYNCHRONIZATION TRUE
#endif
/*===========================================================================*/
/* SERIAL_USB driver related setting. */
/*===========================================================================*/
@@ -451,11 +471,10 @@
#endif
/**
* @brief Enables circular transfers APIs.
* @note Disabling this option saves both code and data space.
* @brief Inserts an assertion on function errors before returning.
*/
#if !defined(SPI_USE_CIRCULAR) || defined(__DOXYGEN__)
#define SPI_USE_CIRCULAR FALSE
#if !defined(SPI_USE_ASSERT_ON_ERROR) || defined(__DOXYGEN__)
#define SPI_USE_ASSERT_ON_ERROR TRUE
#endif
/**

0
platforms/chibios/boards/BLACKPILL_STM32_F401/ld/STM32F401xC_tinyuf2.ld → platforms/chibios/boards/common/ld/STM32F401xC_tinyuf2.ld
View File

0
platforms/chibios/boards/BLACKPILL_STM32_F401/ld/STM32F401xE_tinyuf2.ld → platforms/chibios/boards/common/ld/STM32F401xE_tinyuf2.ld
View File

0
platforms/chibios/boards/BLACKPILL_STM32_F411/ld/STM32F411xC_tinyuf2.ld → platforms/chibios/boards/common/ld/STM32F411xC_tinyuf2.ld
View File

0
platforms/chibios/boards/BLACKPILL_STM32_F411/ld/STM32F411xE_tinyuf2.ld → platforms/chibios/boards/common/ld/STM32F411xE_tinyuf2.ld
View File

1
platforms/chibios/bootloaders/custom.c
View File

@@ -17,5 +17,6 @@
#include "bootloader.h"
__attribute__((weak)) void bootloader_jump(void) {}
__attribute__((weak)) void mcu_reset(void) {}
__attribute__((weak)) void enter_bootloader_mode_if_requested(void) {}

7
platforms/chibios/bootloaders/gd32v_dfu.c
View File

@@ -36,5 +36,12 @@ __attribute__((weak)) void bootloader_jump(void) {
*DBGMCU_CMD = DBGMCU_CMD_RESET;
}
__attribute__((weak)) void mcu_reset(void) {
// Confirmed by karlk90, there is no actual reset to bootloader.
// This just resets the controller.
*DBGMCU_KEY = DBGMCU_KEY_UNLOCK;
*DBGMCU_CMD = DBGMCU_CMD_RESET;
}
/* Jumping to bootloader is not possible from user code. */
void enter_bootloader_mode_if_requested(void) {}

2
platforms/chibios/bootloaders/halfkay.c
View File

@@ -23,3 +23,5 @@ __attribute__((weak)) void bootloader_jump(void) {
wait_ms(100);
__BKPT(0);
}
__attribute__((weak)) void mcu_reset(void) {}

1
platforms/chibios/bootloaders/kiibohd.c
View File

@@ -30,3 +30,4 @@ __attribute__((weak)) void bootloader_jump(void) {
// request reset
SCB->AIRCR = SCB_AIRCR_VECTKEY_WRITEMAGIC | SCB_AIRCR_SYSRESETREQ_Msk;
}
__attribute__((weak)) void mcu_reset(void) {}

7
platforms/chibios/bootloaders/stm32_dfu.c
View File

@@ -61,6 +61,9 @@ __attribute__((weak)) void bootloader_jump(void) {
NVIC_SystemReset();
}
__attribute__((weak)) void mcu_reset(void) {
NVIC_SystemReset();
}
// not needed at all, but if anybody attempts to invoke it....
void enter_bootloader_mode_if_requested(void) {}
@@ -76,6 +79,10 @@ __attribute__((weak)) void bootloader_jump(void) {
NVIC_SystemReset();
}
__attribute__((weak)) void mcu_reset(void) {
NVIC_SystemReset();
}
void enter_bootloader_mode_if_requested(void) {
unsigned long *check = MAGIC_ADDR;
if (*check == BOOTLOADER_MAGIC) {

5
platforms/chibios/bootloaders/stm32duino.c
View File

@@ -21,3 +21,8 @@
__attribute__((weak)) void bootloader_jump(void) {
NVIC_SystemReset();
}
__attribute__((weak)) void mcu_reset(void) {
BKP->DR10 = RTC_BOOTLOADER_JUST_UPLOADED;
NVIC_SystemReset();
}

4
platforms/chibios/bootloaders/tinyuf2.c
View File

@@ -25,6 +25,10 @@
extern uint32_t _board_dfu_dbl_tap[];
#define DBL_TAP_REG _board_dfu_dbl_tap[0]
__attribute__((weak)) void mcu_reset(void) {
NVIC_SystemReset();
}
__attribute__((weak)) void bootloader_jump(void) {
DBL_TAP_REG = DBL_TAP_MAGIC;
NVIC_SystemReset();

53
platforms/chibios/bootloaders/wb32_dfu.c Normal file
View File

@@ -0,0 +1,53 @@
/* Copyright 2021 QMK
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#include "bootloader.h"
#include <ch.h>
#include <hal.h>
#include "wait.h"
extern uint32_t __ram0_end__;
/* This code should be checked whether it runs correctly on platforms */
#define SYMVAL(sym) (uint32_t)(((uint8_t *)&(sym)) - ((uint8_t *)0))
#define BOOTLOADER_MAGIC 0xDEADBEEF
#define MAGIC_ADDR (unsigned long *)(SYMVAL(__ram0_end__) - 4)
__attribute__((weak)) void bootloader_jump(void) {
*MAGIC_ADDR = BOOTLOADER_MAGIC; // set magic flag => reset handler will jump into boot loader
NVIC_SystemReset();
}
void enter_bootloader_mode_if_requested(void) {
unsigned long *check = MAGIC_ADDR;
if (*check == BOOTLOADER_MAGIC) {
*check = 0;
__set_CONTROL(0);
__set_MSP(*(__IO uint32_t *)WB32_BOOTLOADER_ADDRESS);
__enable_irq();
typedef void (*BootJump_t)(void);
BootJump_t boot_jump = *(BootJump_t *)(WB32_BOOTLOADER_ADDRESS + 4);
boot_jump();
while (1)
;
}
}
__attribute__((weak)) void mcu_reset(void) {
NVIC_SystemReset();
}

2
platforms/chibios/chibios_config.h
View File

@@ -55,7 +55,7 @@
#if defined(MCU_WB32)
# define CPU_CLOCK WB32_MAINCLK
# if defined(WB32F3G71xx)
# if defined(WB32F3G71xx) || defined(WB32FQ95xx)
# define PAL_OUTPUT_TYPE_OPENDRAIN PAL_WB32_OTYPE_OPENDRAIN
# define PAL_OUTPUT_TYPE_PUSHPULL PAL_WB32_OTYPE_PUSHPULL
# define PAL_OUTPUT_SPEED_HIGHEST PAL_WB32_OSPEED_HIGH

41
platforms/chibios/converters/promicro_to_proton_c/_pin_defs.h Normal file
View File

@@ -0,0 +1,41 @@
// Copyright 2022 QMK
// SPDX-License-Identifier: GPL-2.0-or-later
#pragma once
// Left side (front)
#define D3 PAL_LINE(GPIOA, 9)
#define D2 PAL_LINE(GPIOA, 10)
// GND
// GND
#define D1 PAL_LINE(GPIOB, 7)
#define D0 PAL_LINE(GPIOB, 6)
#define D4 PAL_LINE(GPIOB, 5)
#define C6 PAL_LINE(GPIOB, 4)
#define D7 PAL_LINE(GPIOB, 3)
#define E6 PAL_LINE(GPIOB, 2)
#define B4 PAL_LINE(GPIOB, 1)
#define B5 PAL_LINE(GPIOB, 0)
// Right side (front)
// RAW
// GND
// RESET
// VCC
#define F4 PAL_LINE(GPIOA, 2)
#define F5 PAL_LINE(GPIOA, 1)
#define F6 PAL_LINE(GPIOA, 0)
#define F7 PAL_LINE(GPIOB, 8)
#define B1 PAL_LINE(GPIOB, 13)
#define B3 PAL_LINE(GPIOB, 14)
#define B2 PAL_LINE(GPIOB, 15)
#define B6 PAL_LINE(GPIOB, 9)
// LEDs (only D5/C13 uses an actual LED)
#ifdef CONVERT_TO_PROTON_C_RXLED
# define D5 PAL_LINE(GPIOC, 14)
# define B0 PAL_LINE(GPIOC, 13)
#else
# define D5 PAL_LINE(GPIOC, 13)
# define B0 PAL_LINE(GPIOC, 14)
#endif

2
platforms/chibios/boards/QMK_PROTON_C/convert_to_proton_c.mk → platforms/chibios/converters/promicro_to_proton_c/converter.mk
View File

@@ -1,9 +1,7 @@
# Proton C MCU settings for converting AVR projects
TARGET := $(TARGET)_proton_c
MCU := STM32F303
BOARD := QMK_PROTON_C
BOOTLOADER := stm32-dfu
OPT_DEFS += -DCONVERT_TO_PROTON_C
# These are defaults based on what has been implemented for ARM boards
AUDIO_ENABLE ?= yes

2
platforms/chibios/drivers/i2c_master.c
View File

@@ -97,7 +97,7 @@ static const I2CConfig i2cconfig = {
I2C1_OPMODE,
I2C1_CLOCK_SPEED,
I2C1_DUTY_CYCLE,
#elif defined(WB32F3G71xx)
#elif defined(WB32F3G71xx) || defined(WB32FQ95xx)
I2C1_OPMODE,
I2C1_CLOCK_SPEED,
#else

29
platforms/chibios/drivers/serial.c
View File

@@ -5,6 +5,7 @@
#include "quantum.h"
#include "serial.h"
#include "wait.h"
#include "synchronization_util.h"
#include <hal.h>
@@ -86,7 +87,10 @@ static THD_FUNCTION(Thread1, arg) {
chRegSetThreadName("blinker");
while (true) {
palWaitLineTimeout(SOFT_SERIAL_PIN, TIME_INFINITE);
split_shared_memory_lock();
interrupt_handler(NULL);
split_shared_memory_unlock();
}
}
@@ -205,14 +209,9 @@ void interrupt_handler(void *arg) {
chSysUnlockFromISR();
}
/////////
// start transaction by initiator
//
// bool soft_serial_transaction(int sstd_index)
//
// this code is very time dependent, so we need to disable interrupts
bool soft_serial_transaction(int sstd_index) {
static inline bool initiate_transaction(uint8_t sstd_index) {
if (sstd_index > NUM_TOTAL_TRANSACTIONS) return false;
split_transaction_desc_t *trans = &split_transaction_table[sstd_index];
// TODO: remove extra delay between transactions
@@ -239,8 +238,7 @@ bool soft_serial_transaction(int sstd_index) {
return false;
}
// if the slave is present syncronize with it
// if the slave is present synchronize with it
uint8_t checksum = 0;
// send data to the slave
serial_write_byte(sstd_index); // first chunk is transaction id
@@ -286,3 +284,16 @@ bool soft_serial_transaction(int sstd_index) {
chSysUnlock();
return true;
}
/////////
// start transaction by initiator
//
// bool soft_serial_transaction(int sstd_index)
//
// this code is very time dependent, so we need to disable interrupts
bool soft_serial_transaction(int sstd_index) {
split_shared_memory_lock();
bool result = initiate_transaction((uint8_t)sstd_index);
split_shared_memory_unlock();
return result;
}

10
platforms/chibios/drivers/serial_usart.c
View File

@@ -15,6 +15,7 @@
*/
#include "serial_usart.h"
#include "synchronization_util.h"
#if defined(SERIAL_USART_CONFIG)
static SerialConfig serial_config = SERIAL_USART_CONFIG;
@@ -173,6 +174,7 @@ static THD_FUNCTION(SlaveThread, arg) {
* Parts of failed transactions or spurious bytes could still be in it. */
usart_clear();
}
split_shared_memory_unlock();
}
}
@@ -200,6 +202,7 @@ static inline bool react_to_transactions(void) {
return false;
}
split_shared_memory_lock();
split_transaction_desc_t* trans = &split_transaction_table[sstd_index];
/* Send back the handshake which is XORed as a simple checksum,
@@ -254,7 +257,12 @@ bool soft_serial_transaction(int index) {
/* Clear the receive queue, to start with a clean slate.
* Parts of failed transactions or spurious bytes could still be in it. */
usart_clear();
return initiate_transaction((uint8_t)index);
split_shared_memory_lock();
bool result = initiate_transaction((uint8_t)index);
split_shared_memory_unlock();
return result;
}
/**

4
platforms/chibios/drivers/spi_master.c
View File

@@ -54,7 +54,7 @@ bool spi_start(pin_t slavePin, bool lsbFirst, uint8_t mode, uint16_t divisor) {
return false;
}
#ifndef WB32F3G71xx
#if !(defined(WB32F3G71xx) || defined(WB32FQ95xx))
uint16_t roundedDivisor = 2;
while (roundedDivisor < divisor) {
roundedDivisor <<= 1;
@@ -138,7 +138,7 @@ bool spi_start(pin_t slavePin, bool lsbFirst, uint8_t mode, uint16_t divisor) {
spiConfig.cpr = (roundedDivisor - 1) >> 1;
#elif defined(WB32F3G71xx)
#elif defined(WB32F3G71xx) || defined(WB32FQ95xx)
if (!lsbFirst) {
osalDbgAssert(lsbFirst != FALSE, "unsupported lsbFirst");
}

2
platforms/chibios/drivers/uart.c
View File

@@ -18,7 +18,7 @@
#include "quantum.h"
#if defined(WB32F3G71xx)
#if defined(WB32F3G71xx) || defined(WB32FQ95xx)
static SerialConfig serialConfig = {SERIAL_DEFAULT_BITRATE, SD1_WRDLEN, SD1_STPBIT, SD1_PARITY, SD1_ATFLCT};
#else
static SerialConfig serialConfig = {SERIAL_DEFAULT_BITRATE, SD1_CR1, SD1_CR2, SD1_CR3};

28
platforms/chibios/drivers/ws2812_spi.c
View File

@@ -139,7 +139,33 @@ void ws2812_init(void) {
#endif // WS2812_SPI_SCK_PIN
// TODO: more dynamic baudrate
static const SPIConfig spicfg = {WS2812_SPI_BUFFER_MODE, NULL, PAL_PORT(RGB_DI_PIN), PAL_PAD(RGB_DI_PIN), WS2812_SPI_DIVISOR_CR1_BR_X};
static const SPIConfig spicfg = {
#ifndef HAL_LLD_SELECT_SPI_V2
// HAL_SPI_V1
# if SPI_SUPPORTS_CIRCULAR == TRUE
WS2812_SPI_BUFFER_MODE,
# endif
NULL, // end_cb
PAL_PORT(RGB_DI_PIN),
PAL_PAD(RGB_DI_PIN),
WS2812_SPI_DIVISOR_CR1_BR_X,
0
#else
// HAL_SPI_V2
# if SPI_SUPPORTS_CIRCULAR == TRUE
WS2812_SPI_BUFFER_MODE,
# endif
# if SPI_SUPPORTS_SLAVE_MODE == TRUE
false,
# endif
NULL, // data_cb
NULL, // error_cb
PAL_PORT(RGB_DI_PIN),
PAL_PAD(RGB_DI_PIN),
WS2812_SPI_DIVISOR_CR1_BR_X,
0
#endif
};
spiAcquireBus(&WS2812_SPI); /* Acquire ownership of the bus. */
spiStart(&WS2812_SPI, &spicfg); /* Setup transfer parameters. */

4
platforms/chibios/eeprom_stm32_defs.h
View File

@@ -25,7 +25,7 @@
# ifndef FEE_PAGE_COUNT
# define FEE_PAGE_COUNT 2 // How many pages are used
# endif
# elif defined(STM32F103xE) || defined(STM32F303xC) || defined(STM32F072xB) || defined(STM32F070xB)
# elif defined(STM32F103xE) || defined(STM32F303xC) || defined(STM32F303xE) || defined(STM32F072xB) || defined(STM32F070xB)
# ifndef FEE_PAGE_SIZE
# define FEE_PAGE_SIZE 0x800 // Page size = 2KByte
# endif
@@ -51,7 +51,7 @@
# define FEE_MCU_FLASH_SIZE 128 // Size in Kb
# elif defined(STM32F303xC) || defined(STM32F401xC)
# define FEE_MCU_FLASH_SIZE 256 // Size in Kb
# elif defined(STM32F103xE) || defined(STM32F401xE) || defined(STM32F411xE)
# elif defined(STM32F103xE) || defined(STM32F303xE) || defined(STM32F401xE) || defined(STM32F411xE)
# define FEE_MCU_FLASH_SIZE 512 // Size in Kb
# elif defined(STM32F405xG)
# define FEE_MCU_FLASH_SIZE 1024 // Size in Kb

14
platforms/chibios/flash.mk
View File

@@ -40,6 +40,18 @@ endef
dfu-util: $(BUILD_DIR)/$(TARGET).bin cpfirmware sizeafter
$(call EXEC_DFU_UTIL)
define EXEC_UF2_UTIL_DEPLOY
if ! $(UF2CONV) --deploy $(BUILD_DIR)/$(TARGET).uf2 2>/dev/null; then \
printf "$(MSG_BOOTLOADER_NOT_FOUND_QUICK_RETRY)" ;\
sleep $(BOOTLOADER_RETRY_TIME) ;\
while ! $(UF2CONV) --deploy $(BUILD_DIR)/$(TARGET).uf2 2>/dev/null; do \
printf "." ;\
sleep $(BOOTLOADER_RETRY_TIME) ;\
done ;\
printf "\n" ;\
fi
endef
# TODO: Remove once ARM has a way to configure EECONFIG_HANDEDNESS
# within the emulated eeprom via dfu-util or another tool
ifneq (,$(filter $(MAKECMDGOALS),dfu-util-split-left))
@@ -90,6 +102,8 @@ ifneq ($(strip $(PROGRAM_CMD)),)
$(UNSYNC_OUTPUT_CMD) && $(PROGRAM_CMD)
else ifeq ($(strip $(BOOTLOADER)),kiibohd)
$(UNSYNC_OUTPUT_CMD) && $(call EXEC_DFU_UTIL)
else ifeq ($(strip $(BOOTLOADER)),tinyuf2)
$(UNSYNC_OUTPUT_CMD) && $(call EXEC_UF2_UTIL_DEPLOY)
else ifeq ($(strip $(MCU_FAMILY)),KINETIS)
$(UNSYNC_OUTPUT_CMD) && $(call EXEC_TEENSY)
else ifeq ($(strip $(MCU_FAMILY)),MIMXRT1062)

9
platforms/chibios/gpio.h
View File

@@ -31,7 +31,14 @@ typedef ioline_t pin_t;
#define writePinHigh(pin) palSetLine(pin)
#define writePinLow(pin) palClearLine(pin)
#define writePin(pin, level) ((level) ? (writePinHigh(pin)) : (writePinLow(pin)))
#define writePin(pin, level) \
do { \
if (level) { \
writePinHigh(pin); \
} else { \
writePinLow(pin); \
} \
} while (0)
#define readPin(pin) palReadLine(pin)

15
platforms/chibios/hardware_id.c Normal file
View File

@@ -0,0 +1,15 @@
// Copyright 2022 QMK
// SPDX-License-Identifier: GPL-2.0-or-later
#include <ch.h>
#include "hardware_id.h"
hardware_id_t get_hardware_id(void) {
hardware_id_t id = {0};
#ifdef UID_BASE
id.data[0] = (uint32_t)(*((uint32_t *)UID_BASE));
id.data[1] = (uint32_t)(*((uint32_t *)(UID_BASE + 4)));
id.data[1] = (uint32_t)(*((uint32_t *)(UID_BASE + 8)));
#endif
return id;
}

323
platforms/chibios/pin_defs.h
View File

@@ -1,323 +0,0 @@
/* Copyright 2021 QMK
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#pragma once
// Defines mapping for Proton C replacement
#ifdef CONVERT_TO_PROTON_C
// Left side (front)
# define D3 PAL_LINE(GPIOA, 9)
# define D2 PAL_LINE(GPIOA, 10)
// GND
// GND
# define D1 PAL_LINE(GPIOB, 7)
# define D0 PAL_LINE(GPIOB, 6)
# define D4 PAL_LINE(GPIOB, 5)
# define C6 PAL_LINE(GPIOB, 4)
# define D7 PAL_LINE(GPIOB, 3)
# define E6 PAL_LINE(GPIOB, 2)
# define B4 PAL_LINE(GPIOB, 1)
# define B5 PAL_LINE(GPIOB, 0)
// Right side (front)
// RAW
// GND
// RESET
// VCC
# define F4 PAL_LINE(GPIOA, 2)
# define F5 PAL_LINE(GPIOA, 1)
# define F6 PAL_LINE(GPIOA, 0)
# define F7 PAL_LINE(GPIOB, 8)
# define B1 PAL_LINE(GPIOB, 13)
# define B3 PAL_LINE(GPIOB, 14)
# define B2 PAL_LINE(GPIOB, 15)
# define B6 PAL_LINE(GPIOB, 9)
// LEDs (only D5/C13 uses an actual LED)
# ifdef CONVERT_TO_PROTON_C_RXLED
# define D5 PAL_LINE(GPIOC, 14)
# define B0 PAL_LINE(GPIOC, 13)
# else
# define D5 PAL_LINE(GPIOC, 13)
# define B0 PAL_LINE(GPIOC, 14)
# endif
#else
# define A0 PAL_LINE(GPIOA, 0)
# define A1 PAL_LINE(GPIOA, 1)
# define A2 PAL_LINE(GPIOA, 2)
# define A3 PAL_LINE(GPIOA, 3)
# define A4 PAL_LINE(GPIOA, 4)
# define A5 PAL_LINE(GPIOA, 5)
# define A6 PAL_LINE(GPIOA, 6)
# define A7 PAL_LINE(GPIOA, 7)
# define A8 PAL_LINE(GPIOA, 8)
# define A9 PAL_LINE(GPIOA, 9)
# define A10 PAL_LINE(GPIOA, 10)
# define A11 PAL_LINE(GPIOA, 11)
# define A12 PAL_LINE(GPIOA, 12)
# define A13 PAL_LINE(GPIOA, 13)
# define A14 PAL_LINE(GPIOA, 14)
# define A15 PAL_LINE(GPIOA, 15)
# define A16 PAL_LINE(GPIOA, 16)
# define A17 PAL_LINE(GPIOA, 17)
# define A18 PAL_LINE(GPIOA, 18)
# define A19 PAL_LINE(GPIOA, 19)
# define A20 PAL_LINE(GPIOA, 20)
# define A21 PAL_LINE(GPIOA, 21)
# define A22 PAL_LINE(GPIOA, 22)
# define A23 PAL_LINE(GPIOA, 23)
# define A24 PAL_LINE(GPIOA, 24)
# define A25 PAL_LINE(GPIOA, 25)
# define A26 PAL_LINE(GPIOA, 26)
# define A27 PAL_LINE(GPIOA, 27)
# define A28 PAL_LINE(GPIOA, 28)
# define A29 PAL_LINE(GPIOA, 29)
# define A30 PAL_LINE(GPIOA, 30)
# define A31 PAL_LINE(GPIOA, 31)
# define A32 PAL_LINE(GPIOA, 32)
# define B0 PAL_LINE(GPIOB, 0)
# define B1 PAL_LINE(GPIOB, 1)
# define B2 PAL_LINE(GPIOB, 2)
# define B3 PAL_LINE(GPIOB, 3)
# define B4 PAL_LINE(GPIOB, 4)
# define B5 PAL_LINE(GPIOB, 5)
# define B6 PAL_LINE(GPIOB, 6)
# define B7 PAL_LINE(GPIOB, 7)
# define B8 PAL_LINE(GPIOB, 8)
# define B9 PAL_LINE(GPIOB, 9)
# define B10 PAL_LINE(GPIOB, 10)
# define B11 PAL_LINE(GPIOB, 11)
# define B12 PAL_LINE(GPIOB, 12)
# define B13 PAL_LINE(GPIOB, 13)
# define B14 PAL_LINE(GPIOB, 14)
# define B15 PAL_LINE(GPIOB, 15)
# define B16 PAL_LINE(GPIOB, 16)
# define B17 PAL_LINE(GPIOB, 17)
# define B18 PAL_LINE(GPIOB, 18)
# define B19 PAL_LINE(GPIOB, 19)
# define B20 PAL_LINE(GPIOB, 20)
# define B21 PAL_LINE(GPIOB, 21)
# define B22 PAL_LINE(GPIOB, 22)
# define B23 PAL_LINE(GPIOB, 23)
# define B24 PAL_LINE(GPIOB, 24)
# define B25 PAL_LINE(GPIOB, 25)
# define B26 PAL_LINE(GPIOB, 26)
# define B27 PAL_LINE(GPIOB, 27)
# define B28 PAL_LINE(GPIOB, 28)
# define B29 PAL_LINE(GPIOB, 29)
# define B30 PAL_LINE(GPIOB, 30)
# define B31 PAL_LINE(GPIOB, 31)
# define B32 PAL_LINE(GPIOB, 32)
# define C0 PAL_LINE(GPIOC, 0)
# define C1 PAL_LINE(GPIOC, 1)
# define C2 PAL_LINE(GPIOC, 2)
# define C3 PAL_LINE(GPIOC, 3)
# define C4 PAL_LINE(GPIOC, 4)
# define C5 PAL_LINE(GPIOC, 5)
# define C6 PAL_LINE(GPIOC, 6)
# define C7 PAL_LINE(GPIOC, 7)
# define C8 PAL_LINE(GPIOC, 8)
# define C9 PAL_LINE(GPIOC, 9)
# define C10 PAL_LINE(GPIOC, 10)
# define C11 PAL_LINE(GPIOC, 11)
# define C12 PAL_LINE(GPIOC, 12)
# define C13 PAL_LINE(GPIOC, 13)
# define C14 PAL_LINE(GPIOC, 14)
# define C15 PAL_LINE(GPIOC, 15)
# define C16 PAL_LINE(GPIOC, 16)
# define C17 PAL_LINE(GPIOC, 17)
# define C18 PAL_LINE(GPIOC, 18)
# define C19 PAL_LINE(GPIOC, 19)
# define C20 PAL_LINE(GPIOC, 20)
# define C21 PAL_LINE(GPIOC, 21)
# define C22 PAL_LINE(GPIOC, 22)
# define C23 PAL_LINE(GPIOC, 23)
# define C24 PAL_LINE(GPIOC, 24)
# define C25 PAL_LINE(GPIOC, 25)
# define C26 PAL_LINE(GPIOC, 26)
# define C27 PAL_LINE(GPIOC, 27)
# define C28 PAL_LINE(GPIOC, 28)
# define C29 PAL_LINE(GPIOC, 29)
# define C30 PAL_LINE(GPIOC, 30)
# define C31 PAL_LINE(GPIOC, 31)
# define C32 PAL_LINE(GPIOC, 32)
# define D0 PAL_LINE(GPIOD, 0)
# define D1 PAL_LINE(GPIOD, 1)
# define D2 PAL_LINE(GPIOD, 2)
# define D3 PAL_LINE(GPIOD, 3)
# define D4 PAL_LINE(GPIOD, 4)
# define D5 PAL_LINE(GPIOD, 5)
# define D6 PAL_LINE(GPIOD, 6)
# define D7 PAL_LINE(GPIOD, 7)
# define D8 PAL_LINE(GPIOD, 8)
# define D9 PAL_LINE(GPIOD, 9)
# define D10 PAL_LINE(GPIOD, 10)
# define D11 PAL_LINE(GPIOD, 11)
# define D12 PAL_LINE(GPIOD, 12)
# define D13 PAL_LINE(GPIOD, 13)
# define D14 PAL_LINE(GPIOD, 14)
# define D15 PAL_LINE(GPIOD, 15)
# define D16 PAL_LINE(GPIOD, 16)
# define D17 PAL_LINE(GPIOD, 17)
# define D18 PAL_LINE(GPIOD, 18)
# define D19 PAL_LINE(GPIOD, 19)
# define D20 PAL_LINE(GPIOD, 20)
# define D21 PAL_LINE(GPIOD, 21)
# define D22 PAL_LINE(GPIOD, 22)
# define D23 PAL_LINE(GPIOD, 23)
# define D24 PAL_LINE(GPIOD, 24)
# define D25 PAL_LINE(GPIOD, 25)
# define D26 PAL_LINE(GPIOD, 26)
# define D27 PAL_LINE(GPIOD, 27)
# define D28 PAL_LINE(GPIOD, 28)
# define D29 PAL_LINE(GPIOD, 29)
# define D30 PAL_LINE(GPIOD, 30)
# define D31 PAL_LINE(GPIOD, 31)
# define D32 PAL_LINE(GPIOD, 32)
# define E0 PAL_LINE(GPIOE, 0)
# define E1 PAL_LINE(GPIOE, 1)
# define E2 PAL_LINE(GPIOE, 2)
# define E3 PAL_LINE(GPIOE, 3)
# define E4 PAL_LINE(GPIOE, 4)
# define E5 PAL_LINE(GPIOE, 5)
# define E6 PAL_LINE(GPIOE, 6)
# define E7 PAL_LINE(GPIOE, 7)
# define E8 PAL_LINE(GPIOE, 8)
# define E9 PAL_LINE(GPIOE, 9)
# define E10 PAL_LINE(GPIOE, 10)
# define E11 PAL_LINE(GPIOE, 11)
# define E12 PAL_LINE(GPIOE, 12)
# define E13 PAL_LINE(GPIOE, 13)
# define E14 PAL_LINE(GPIOE, 14)
# define E15 PAL_LINE(GPIOE, 15)
# define E16 PAL_LINE(GPIOE, 16)
# define E17 PAL_LINE(GPIOE, 17)
# define E18 PAL_LINE(GPIOE, 18)
# define E19 PAL_LINE(GPIOE, 19)
# define E20 PAL_LINE(GPIOE, 20)
# define E21 PAL_LINE(GPIOE, 21)
# define E22 PAL_LINE(GPIOE, 22)
# define E23 PAL_LINE(GPIOE, 23)
# define E24 PAL_LINE(GPIOE, 24)
# define E25 PAL_LINE(GPIOE, 25)
# define E26 PAL_LINE(GPIOE, 26)
# define E27 PAL_LINE(GPIOE, 27)
# define E28 PAL_LINE(GPIOE, 28)
# define E29 PAL_LINE(GPIOE, 29)
# define E30 PAL_LINE(GPIOE, 30)
# define E31 PAL_LINE(GPIOE, 31)
# define E32 PAL_LINE(GPIOE, 32)
# define F0 PAL_LINE(GPIOF, 0)
# define F1 PAL_LINE(GPIOF, 1)
# define F2 PAL_LINE(GPIOF, 2)
# define F3 PAL_LINE(GPIOF, 3)
# define F4 PAL_LINE(GPIOF, 4)
# define F5 PAL_LINE(GPIOF, 5)
# define F6 PAL_LINE(GPIOF, 6)
# define F7 PAL_LINE(GPIOF, 7)
# define F8 PAL_LINE(GPIOF, 8)
# define F9 PAL_LINE(GPIOF, 9)
# define F10 PAL_LINE(GPIOF, 10)
# define F11 PAL_LINE(GPIOF, 11)
# define F12 PAL_LINE(GPIOF, 12)
# define F13 PAL_LINE(GPIOF, 13)
# define F14 PAL_LINE(GPIOF, 14)
# define F15 PAL_LINE(GPIOF, 15)
# define G0 PAL_LINE(GPIOG, 0)
# define G1 PAL_LINE(GPIOG, 1)
# define G2 PAL_LINE(GPIOG, 2)
# define G3 PAL_LINE(GPIOG, 3)
# define G4 PAL_LINE(GPIOG, 4)
# define G5 PAL_LINE(GPIOG, 5)
# define G6 PAL_LINE(GPIOG, 6)
# define G7 PAL_LINE(GPIOG, 7)
# define G8 PAL_LINE(GPIOG, 8)
# define G9 PAL_LINE(GPIOG, 9)
# define G10 PAL_LINE(GPIOG, 10)
# define G11 PAL_LINE(GPIOG, 11)
# define G12 PAL_LINE(GPIOG, 12)
# define G13 PAL_LINE(GPIOG, 13)
# define G14 PAL_LINE(GPIOG, 14)
# define G15 PAL_LINE(GPIOG, 15)
# define H0 PAL_LINE(GPIOH, 0)
# define H1 PAL_LINE(GPIOH, 1)
# define H2 PAL_LINE(GPIOH, 2)
# define H3 PAL_LINE(GPIOH, 3)
# define H4 PAL_LINE(GPIOH, 4)
# define H5 PAL_LINE(GPIOH, 5)
# define H6 PAL_LINE(GPIOH, 6)
# define H7 PAL_LINE(GPIOH, 7)
# define H8 PAL_LINE(GPIOH, 8)
# define H9 PAL_LINE(GPIOH, 9)
# define H10 PAL_LINE(GPIOH, 10)
# define H11 PAL_LINE(GPIOH, 11)
# define H12 PAL_LINE(GPIOH, 12)
# define H13 PAL_LINE(GPIOH, 13)
# define H14 PAL_LINE(GPIOH, 14)
# define H15 PAL_LINE(GPIOH, 15)
# define I0 PAL_LINE(GPIOI, 0)
# define I1 PAL_LINE(GPIOI, 1)
# define I2 PAL_LINE(GPIOI, 2)
# define I3 PAL_LINE(GPIOI, 3)
# define I4 PAL_LINE(GPIOI, 4)
# define I5 PAL_LINE(GPIOI, 5)
# define I6 PAL_LINE(GPIOI, 6)
# define I7 PAL_LINE(GPIOI, 7)
# define I8 PAL_LINE(GPIOI, 8)
# define I9 PAL_LINE(GPIOI, 9)
# define I10 PAL_LINE(GPIOI, 10)
# define I11 PAL_LINE(GPIOI, 11)
# define I12 PAL_LINE(GPIOI, 12)
# define I13 PAL_LINE(GPIOI, 13)
# define I14 PAL_LINE(GPIOI, 14)
# define I15 PAL_LINE(GPIOI, 15)
# define J0 PAL_LINE(GPIOJ, 0)
# define J1 PAL_LINE(GPIOJ, 1)
# define J2 PAL_LINE(GPIOJ, 2)
# define J3 PAL_LINE(GPIOJ, 3)
# define J4 PAL_LINE(GPIOJ, 4)
# define J5 PAL_LINE(GPIOJ, 5)
# define J6 PAL_LINE(GPIOJ, 6)
# define J7 PAL_LINE(GPIOJ, 7)
# define J8 PAL_LINE(GPIOJ, 8)
# define J9 PAL_LINE(GPIOJ, 9)
# define J10 PAL_LINE(GPIOJ, 10)
# define J11 PAL_LINE(GPIOJ, 11)
# define J12 PAL_LINE(GPIOJ, 12)
# define J13 PAL_LINE(GPIOJ, 13)
# define J14 PAL_LINE(GPIOJ, 14)
# define J15 PAL_LINE(GPIOJ, 15)
// Keyboards can `#define KEYBOARD_REQUIRES_GPIOK` if they need to access GPIO-K pins. These conflict with a whole
// bunch of layout definitions, so it's intentionally left out unless absolutely required -- in that case, the
// keyboard designer should use a different symbol when defining their layout macros.
# ifdef KEYBOARD_REQUIRES_GPIOK
# define K0 PAL_LINE(GPIOK, 0)
# define K1 PAL_LINE(GPIOK, 1)
# define K2 PAL_LINE(GPIOK, 2)
# define K3 PAL_LINE(GPIOK, 3)
# define K4 PAL_LINE(GPIOK, 4)
# define K5 PAL_LINE(GPIOK, 5)
# define K6 PAL_LINE(GPIOK, 6)
# define K7 PAL_LINE(GPIOK, 7)
# define K8 PAL_LINE(GPIOK, 8)
# define K9 PAL_LINE(GPIOK, 9)
# define K10 PAL_LINE(GPIOK, 10)
# define K11 PAL_LINE(GPIOK, 11)
# define K12 PAL_LINE(GPIOK, 12)
# define K13 PAL_LINE(GPIOK, 13)
# define K14 PAL_LINE(GPIOK, 14)
# define K15 PAL_LINE(GPIOK, 15)
# endif
#endif

16
platforms/chibios/platform.mk
View File

@@ -39,7 +39,6 @@ ifeq ($(strip $(MCU)), risc-v)
STARTUP_MK = $(CHIBIOS_CONTRIB)/os/common/startup/RISCV-ECLIC/compilers/GCC/mk/startup_$(MCU_STARTUP).mk
PORT_V = $(CHIBIOS_CONTRIB)/os/common/ports/RISCV-ECLIC/compilers/GCC/mk/port.mk
RULESPATH = $(CHIBIOS_CONTRIB)/os/common/startup/RISCV-ECLIC/compilers/GCC
PLATFORM_MK = $(CHIBIOS_CONTRIB)/os/hal/ports/GD/GD32VF103/platform.mk
else
# ARM Support
CHIBIOS_PORT ?=
@@ -82,10 +81,15 @@ ifeq ("$(PLATFORM_NAME)","")
PLATFORM_NAME = platform
endif
# If no MCU port name was specified, use the family instead
ifeq ("$(MCU_PORT_NAME)","")
MCU_PORT_NAME = $(MCU_FAMILY)
endif
ifeq ("$(wildcard $(PLATFORM_MK))","")
PLATFORM_MK = $(CHIBIOS)/os/hal/ports/$(MCU_FAMILY)/$(MCU_SERIES)/$(PLATFORM_NAME).mk
PLATFORM_MK = $(CHIBIOS)/os/hal/ports/$(MCU_PORT_NAME)/$(MCU_SERIES)/$(PLATFORM_NAME).mk
ifeq ("$(wildcard $(PLATFORM_MK))","")
PLATFORM_MK = $(CHIBIOS_CONTRIB)/os/hal/ports/$(MCU_FAMILY)/$(MCU_SERIES)/$(PLATFORM_NAME).mk
PLATFORM_MK = $(CHIBIOS_CONTRIB)/os/hal/ports/$(MCU_PORT_NAME)/$(MCU_SERIES)/$(PLATFORM_NAME).mk
endif
endif
@@ -261,7 +265,8 @@ PLATFORM_SRC = \
$(STREAMSSRC) \
$(CHIBIOS)/os/various/syscalls.c \
$(PLATFORM_COMMON_DIR)/syscall-fallbacks.c \
$(PLATFORM_COMMON_DIR)/wait.c
$(PLATFORM_COMMON_DIR)/wait.c \
$(PLATFORM_COMMON_DIR)/synchronization_util.c
# Ensure the ASM files are not subjected to LTO -- it'll strip out interrupt handlers otherwise.
QUANTUM_LIB_SRC += $(STARTUPASM) $(PORTASM) $(OSALASM) $(PLATFORMASM)
@@ -416,6 +421,9 @@ LDFLAGS += $(SHARED_LDFLAGS) $(SHARED_LDSYMBOLS) $(TOOLCHAIN_LDFLAGS) $(TOOLCHA
# Tell QMK that we are hosting it on ChibiOS.
OPT_DEFS += -DPROTOCOL_CHIBIOS
# ChibiOS supports synchronization primitives like a Mutex
OPT_DEFS += -DPLATFORM_SUPPORTS_SYNCHRONIZATION
# Workaround to stop ChibiOS from complaining about new GCC -- it's been fixed for 7/8/9 already
OPT_DEFS += -DPORT_IGNORE_GCC_VERSION_CHECK=1

26
platforms/chibios/synchronization_util.c Normal file
View File

@@ -0,0 +1,26 @@
// Copyright 2022 Stefan Kerkmann
// SPDX-License-Identifier: GPL-2.0-or-later
#include "synchronization_util.h"
#include "ch.h"
#if defined(SPLIT_KEYBOARD)
static MUTEX_DECL(SPLIT_SHARED_MEMORY_MUTEX);
/**
* @brief Acquire exclusive access to the split keyboard shared memory, by
* locking the mutex guarding it. If the mutex is already held, the calling
* thread will be suspended until the mutex currently owning thread releases the
* mutex again.
*/
void split_shared_memory_lock(void) {
chMtxLock(&SPLIT_SHARED_MEMORY_MUTEX);
}
/**
* @brief Release the split shared memory mutex that has been acquired before.
*/
void split_shared_memory_unlock(void) {
chMtxUnlock(&SPLIT_SHARED_MEMORY_MUTEX);
}
#endif

2
platforms/chibios/timer.c
View File

@@ -40,7 +40,7 @@ static virtual_timer_t update_timer;
# define UPDATE_INTERVAL (((sysinterval_t)1) << (CH_CFG_ST_RESOLUTION - 1))
// VT callback function to keep the overflow bits of the system tick counter updated.
static void update_fn(void *arg) {
static void update_fn(struct ch_virtual_timer *timer, void *arg) {
(void)arg;
chSysLockFromISR();
get_system_time_ticks();

2
platforms/chibios/wait.c
View File

@@ -31,7 +31,7 @@ void wait_us(uint16_t duration) {
* Only use this timer on the main thread;
* other threads need to use their own timer.
*/
if (chThdGetSelfX() == &ch.mainthread && duration < (1ULL << (sizeof(gptcnt_t) * 8))) {
if (chThdGetSelfX() == &(currcore->mainthread) && duration < (1ULL << (sizeof(gptcnt_t) * 8))) {
gptStart(&WAIT_US_TIMER, &gpt_cfg);
gptPolledDelay(&WAIT_US_TIMER, duration);
} else {