jbrechtel/qmk_firmware
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Merge commit '6d0a62920410f50d7f6707960ca1ca0c8fd1d1fa' into firmware21

Browse Source
This commit is contained in:
Drashna Jael're
2021-12-07 09:27:44 -08:00
parent 43002bdf77 6d0a629204
commit 7c18b1c9d3
593 changed files with 14869 additions and 17518 deletions
Download Patch File Download Diff File Expand all files Collapse all files

19
platforms/arm_atsam/_timer.h Normal file
View File

@@ -0,0 +1,19 @@
/* Copyright 2021 Simon Arlott
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#pragma once
// The platform is 32-bit, so prefer 32-bit timers to avoid overflow
#define FAST_TIMER_T_SIZE 32

22
platforms/arm_atsam/_wait.h Normal file
View File

@@ -0,0 +1,22 @@
/* Copyright 2021 QMK
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#pragma once
#include "clks.h"
#define wait_ms(ms) CLK_delay_ms(ms)
#define wait_us(us) CLK_delay_us(us)
#define waitInputPinDelay()

37
platforms/arm_atsam/atomic_util.h Normal file
View File

@@ -0,0 +1,37 @@
/* Copyright 2021 QMK
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#pragma once
#include "samd51j18a.h"
static __inline__ uint8_t __interrupt_disable__(void) {
__disable_irq();
return 1;
}
static __inline__ void __interrupt_enable__(const uint8_t *__s) {
__enable_irq();
__asm__ volatile("" ::: "memory");
(void)__s;
}
#define ATOMIC_BLOCK(type) for (type, __ToDo = __interrupt_disable__(); __ToDo; __ToDo = 0)
#define ATOMIC_FORCEON uint8_t sreg_save __attribute__((__cleanup__(__interrupt_enable__))) = 0
#define ATOMIC_BLOCK_RESTORESTATE _Static_assert(0, "ATOMIC_BLOCK_RESTORESTATE not implemented")
#define ATOMIC_BLOCK_FORCEON ATOMIC_BLOCK(ATOMIC_FORCEON)

57
platforms/arm_atsam/bootloader.c Normal file
View File

@@ -0,0 +1,57 @@
/* Copyright 2017 Fred Sundvik
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#include "bootloader.h"
#include "samd51j18a.h"
#include "md_bootloader.h"
// Set watchdog timer to reset. Directs the bootloader to stay in programming mode.
void bootloader_jump(void) {
#ifdef KEYBOARD_massdrop_ctrl
// CTRL keyboards released with bootloader version below must use RAM method. Otherwise use WDT method.
uint8_t ver_ram_method[] = "v2.18Jun 22 2018 17:28:08"; // The version to match (NULL terminated by compiler)
uint8_t *ver_check = ver_ram_method; // Pointer to version match string for traversal
uint8_t *ver_rom = (uint8_t *)0x21A0; // Pointer to address in ROM where this specific bootloader version would exist
while (*ver_check && *ver_rom == *ver_check) { // While there are check version characters to match and bootloader's version matches check's version
ver_check++; // Move check version pointer to next character
ver_rom++; // Move ROM version pointer to next character
}
if (!*ver_check) { // If check version pointer is NULL, all characters have matched
*MAGIC_ADDR = BOOTLOADER_MAGIC; // Set magic number into RAM
NVIC_SystemReset(); // Perform system reset
while (1) {
} // Won't get here
}
#endif
WDT->CTRLA.bit.ENABLE = 0;
while (WDT->SYNCBUSY.bit.ENABLE) {
}
while (WDT->CTRLA.bit.ENABLE) {
}
WDT->CONFIG.bit.WINDOW = 0;
WDT->CONFIG.bit.PER = 0;
WDT->EWCTRL.bit.EWOFFSET = 0;
WDT->CTRLA.bit.ENABLE = 1;
while (WDT->SYNCBUSY.bit.ENABLE) {
}
while (!WDT->CTRLA.bit.ENABLE) {
}
while (1) {
} // Wait on timeout
}

184
platforms/arm_atsam/eeprom.c Normal file
View File

@@ -0,0 +1,184 @@
/* Copyright 2017 Fred Sundvik
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#include "eeprom.h"
#include "debug.h"
#include "samd51j18a.h"
#include "core_cm4.h"
#include "component/nvmctrl.h"
#ifndef EEPROM_SIZE
# include "eeconfig.h"
# define EEPROM_SIZE (((EECONFIG_SIZE + 3) / 4) * 4) // based off eeconfig's current usage, aligned to 4-byte sizes, to deal with LTO
#endif
#ifndef MAX
# define MAX(X, Y) ((X) > (Y) ? (X) : (Y))
#endif
#ifndef BUSY_RETRIES
# define BUSY_RETRIES 10000
#endif
// #define DEBUG_EEPROM_OUTPUT
/*
* Debug print utils
*/
#if defined(DEBUG_EEPROM_OUTPUT)
# define eeprom_printf(fmt, ...) xprintf(fmt, ##__VA_ARGS__);
#else /* NO_DEBUG */
# define eeprom_printf(fmt, ...)
#endif /* NO_DEBUG */
__attribute__((aligned(4))) static uint8_t buffer[EEPROM_SIZE] = {0};
volatile uint8_t * SmartEEPROM8 = (uint8_t *)SEEPROM_ADDR;
static inline bool eeprom_is_busy(void) {
int timeout = BUSY_RETRIES;
while (NVMCTRL->SEESTAT.bit.BUSY && timeout-- > 0)
;
return NVMCTRL->SEESTAT.bit.BUSY;
}
static uint32_t get_virtual_eeprom_size(void) {
// clang-format off
static const uint32_t VIRTUAL_EEPROM_MAP[11][8] = {
/* 4 8 16 32 64 128 256 512 */
/* 0*/ { 0, 0, 0, 0, 0, 0, 0, 0 },
/* 1*/ { 512, 1024, 2048, 4096, 4096, 4096, 4096, 4096 },
/* 2*/ { 512, 1024, 2048, 4096, 8192, 8192, 8192, 8192 },
/* 3*/ { 512, 1024, 2048, 4096, 8192, 16384, 16384, 16384 },
/* 4*/ { 512, 1024, 2048, 4096, 8192, 16384, 16384, 16384 },
/* 5*/ { 512, 1024, 2048, 4096, 8192, 16384, 32768, 32768 },
/* 6*/ { 512, 1024, 2048, 4096, 8192, 16384, 32768, 32768 },
/* 7*/ { 512, 1024, 2048, 4096, 8192, 16384, 32768, 32768 },
/* 8*/ { 512, 1024, 2048, 4096, 8192, 16384, 32768, 32768 },
/* 9*/ { 512, 1024, 2048, 4096, 8192, 16384, 32768, 65536 },
/*10*/ { 512, 1024, 2048, 4096, 8192, 16384, 32768, 65536 },
};
// clang-format on
static uint32_t virtual_eeprom_size = UINT32_MAX;
if (virtual_eeprom_size == UINT32_MAX) {
virtual_eeprom_size = VIRTUAL_EEPROM_MAP[NVMCTRL->SEESTAT.bit.PSZ][NVMCTRL->SEESTAT.bit.SBLK];
}
// eeprom_printf("get_virtual_eeprom_size:: %d:%d:%d\n", NVMCTRL->SEESTAT.bit.PSZ, NVMCTRL->SEESTAT.bit.SBLK, virtual_eeprom_size);
return virtual_eeprom_size;
}
uint8_t eeprom_read_byte(const uint8_t *addr) {
uintptr_t offset = (uintptr_t)addr;
if (offset >= MAX(EEPROM_SIZE, get_virtual_eeprom_size())) {
eeprom_printf("eeprom_read_byte:: out of bounds\n");
return 0x0;
}
if (get_virtual_eeprom_size() == 0) {
return buffer[offset];
}
if (eeprom_is_busy()) {
eeprom_printf("eeprom_write_byte:: timeout\n");
return 0x0;
}
return SmartEEPROM8[offset];
}
void eeprom_write_byte(uint8_t *addr, uint8_t value) {
uintptr_t offset = (uintptr_t)addr;
if (offset >= MAX(EEPROM_SIZE, get_virtual_eeprom_size())) {
eeprom_printf("eeprom_write_byte:: out of bounds\n");
return;
}
if (get_virtual_eeprom_size() == 0) {
buffer[offset] = value;
return;
}
if (eeprom_is_busy()) {
eeprom_printf("eeprom_write_byte:: timeout\n");
return;
}
SmartEEPROM8[offset] = value;
}
uint16_t eeprom_read_word(const uint16_t *addr) {
const uint8_t *p = (const uint8_t *)addr;
return eeprom_read_byte(p) | (eeprom_read_byte(p + 1) << 8);
}
uint32_t eeprom_read_dword(const uint32_t *addr) {
const uint8_t *p = (const uint8_t *)addr;
return eeprom_read_byte(p) | (eeprom_read_byte(p + 1) << 8) | (eeprom_read_byte(p + 2) << 16) | (eeprom_read_byte(p + 3) << 24);
}
void eeprom_read_block(void *buf, const void *addr, size_t len) {
const uint8_t *p = (const uint8_t *)addr;
uint8_t * dest = (uint8_t *)buf;
while (len--) {
*dest++ = eeprom_read_byte(p++);
}
}
void eeprom_write_word(uint16_t *addr, uint16_t value) {
uint8_t *p = (uint8_t *)addr;
eeprom_write_byte(p++, value);
eeprom_write_byte(p, value >> 8);
}
void eeprom_write_dword(uint32_t *addr, uint32_t value) {
uint8_t *p = (uint8_t *)addr;
eeprom_write_byte(p++, value);
eeprom_write_byte(p++, value >> 8);
eeprom_write_byte(p++, value >> 16);
eeprom_write_byte(p, value >> 24);
}
void eeprom_write_block(const void *buf, void *addr, size_t len) {
uint8_t * p = (uint8_t *)addr;
const uint8_t *src = (const uint8_t *)buf;
while (len--) {
eeprom_write_byte(p++, *src++);
}
}
void eeprom_update_byte(uint8_t *addr, uint8_t value) { eeprom_write_byte(addr, value); }
void eeprom_update_word(uint16_t *addr, uint16_t value) {
uint8_t *p = (uint8_t *)addr;
eeprom_write_byte(p++, value);
eeprom_write_byte(p, value >> 8);
}
void eeprom_update_dword(uint32_t *addr, uint32_t value) {
uint8_t *p = (uint8_t *)addr;
eeprom_write_byte(p++, value);
eeprom_write_byte(p++, value >> 8);
eeprom_write_byte(p++, value >> 16);
eeprom_write_byte(p, value >> 24);
}
void eeprom_update_block(const void *buf, void *addr, size_t len) {
uint8_t * p = (uint8_t *)addr;
const uint8_t *src = (const uint8_t *)buf;
while (len--) {
eeprom_write_byte(p++, *src++);
}
}

11
platforms/arm_atsam/flash.mk
View File

@@ -3,9 +3,20 @@
# Architecture or project specific options
#
MDLOADER_CLI ?= mdloader
define EXEC_MDLOADER
$(MDLOADER_CLI) --first --download $(BUILD_DIR)/$(TARGET).bin --restart
endef
mdloader: bin
$(call EXEC_MDLOADER)
flash: bin
ifneq ($(strip $(PROGRAM_CMD)),)
$(UNSYNC_OUTPUT_CMD) && $(PROGRAM_CMD)
else ifeq ($(strip $(ARM_ATSAM)),SAMD51J18A)
$(UNSYNC_OUTPUT_CMD) && $(call EXEC_MDLOADER)
else
$(PRINT_OK); $(SILENT) || printf "$(MSG_FLASH_ARCH)"
endif

77
platforms/arm_atsam/gpio.h Normal file
View File

@@ -0,0 +1,77 @@
/* Copyright 2021 QMK
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#pragma once
#include "stdint.h"
#include "samd51j18a.h"
#include "pin_defs.h"
typedef uint8_t pin_t;
#define SAMD_PORT(pin) ((pin & 0x20) >> 5)
#define SAMD_PIN(pin) (pin & 0x1f)
#define SAMD_PIN_MASK(pin) (1 << (pin & 0x1f))
#define setPinInput(pin) \
do { \
PORT->Group[SAMD_PORT(pin)].PINCFG[SAMD_PIN(pin)].bit.INEN = 1; \
PORT->Group[SAMD_PORT(pin)].DIRCLR.reg = SAMD_PIN_MASK(pin); \
} while (0)
#define setPinInputHigh(pin) \
do { \
PORT->Group[SAMD_PORT(pin)].DIRCLR.reg = SAMD_PIN_MASK(pin); \
PORT->Group[SAMD_PORT(pin)].OUTSET.reg = SAMD_PIN_MASK(pin); \
PORT->Group[SAMD_PORT(pin)].PINCFG[SAMD_PIN(pin)].bit.INEN = 1; \
PORT->Group[SAMD_PORT(pin)].PINCFG[SAMD_PIN(pin)].bit.PULLEN = 1; \
} while (0)
#define setPinInputLow(pin) \
do { \
PORT->Group[SAMD_PORT(pin)].DIRCLR.reg = SAMD_PIN_MASK(pin); \
PORT->Group[SAMD_PORT(pin)].OUTCLR.reg = SAMD_PIN_MASK(pin); \
PORT->Group[SAMD_PORT(pin)].PINCFG[SAMD_PIN(pin)].bit.INEN = 1; \
PORT->Group[SAMD_PORT(pin)].PINCFG[SAMD_PIN(pin)].bit.PULLEN = 1; \
} while (0)
#define setPinOutput(pin) \
do { \
PORT->Group[SAMD_PORT(pin)].DIRSET.reg = SAMD_PIN_MASK(pin); \
PORT->Group[SAMD_PORT(pin)].OUTCLR.reg = SAMD_PIN_MASK(pin); \
} while (0)
#define writePinHigh(pin) \
do { \
PORT->Group[SAMD_PORT(pin)].OUTSET.reg = SAMD_PIN_MASK(pin); \
} while (0)
#define writePinLow(pin) \
do { \
PORT->Group[SAMD_PORT(pin)].OUTCLR.reg = SAMD_PIN_MASK(pin); \
} while (0)
#define writePin(pin, level) \
do { \
if (level) \
PORT->Group[SAMD_PORT(pin)].OUTSET.reg = SAMD_PIN_MASK(pin); \
else \
PORT->Group[SAMD_PORT(pin)].OUTCLR.reg = SAMD_PIN_MASK(pin); \
} while (0)
#define readPin(pin) ((PORT->Group[SAMD_PORT(pin)].IN.reg & SAMD_PIN_MASK(pin)) != 0)
#define togglePin(pin) (PORT->Group[SAMD_PORT(pin)].OUTTGL.reg = SAMD_PIN_MASK(pin))

84
platforms/arm_atsam/pin_defs.h Normal file
View File

@@ -0,0 +1,84 @@
/* Copyright 2021 QMK
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#pragma once
#include "samd51j18a.h"
#define A00 PIN_PA00
#define A01 PIN_PA01
#define A02 PIN_PA02
#define A03 PIN_PA03
#define A04 PIN_PA04
#define A05 PIN_PA05
#define A06 PIN_PA06
#define A07 PIN_PA07
#define A08 PIN_PA08
#define A09 PIN_PA09
#define A10 PIN_PA10
#define A11 PIN_PA11
#define A12 PIN_PA12
#define A13 PIN_PA13
#define A14 PIN_PA14
#define A15 PIN_PA15
#define A16 PIN_PA16
#define A17 PIN_PA17
#define A18 PIN_PA18
#define A19 PIN_PA19
#define A20 PIN_PA20
#define A21 PIN_PA21
#define A22 PIN_PA22
#define A23 PIN_PA23
#define A24 PIN_PA24
#define A25 PIN_PA25
#define A26 PIN_PA26
#define A27 PIN_PA27
#define A28 PIN_PA28
#define A29 PIN_PA29
#define A30 PIN_PA30
#define A31 PIN_PA31
#define B00 PIN_PB00
#define B01 PIN_PB01
#define B02 PIN_PB02
#define B03 PIN_PB03
#define B04 PIN_PB04
#define B05 PIN_PB05
#define B06 PIN_PB06
#define B07 PIN_PB07
#define B08 PIN_PB08
#define B09 PIN_PB09
#define B10 PIN_PB10
#define B11 PIN_PB11
#define B12 PIN_PB12
#define B13 PIN_PB13
#define B14 PIN_PB14
#define B15 PIN_PB15
#define B16 PIN_PB16
#define B17 PIN_PB17
#define B18 PIN_PB18
#define B19 PIN_PB19
#define B20 PIN_PB20
#define B21 PIN_PB21
#define B22 PIN_PB22
#define B23 PIN_PB23
#define B24 PIN_PB24
#define B25 PIN_PB25
#define B26 PIN_PB26
#define B27 PIN_PB27
#define B28 PIN_PB28
#define B29 PIN_PB29
#define B30 PIN_PB30
#define B31 PIN_PB31

21
platforms/arm_atsam/platform.c Normal file
View File

@@ -0,0 +1,21 @@
/* Copyright 2021 QMK
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#include "platform_deps.h"
void platform_setup(void) {
// do nothing
}

67
platforms/arm_atsam/platform.mk Normal file
View File

@@ -0,0 +1,67 @@
# Hey Emacs, this is a -*- makefile -*-
##############################################################################
# Compiler settings
#
CC = $(CC_PREFIX) arm-none-eabi-gcc
OBJCOPY = arm-none-eabi-objcopy
OBJDUMP = arm-none-eabi-objdump
SIZE = arm-none-eabi-size
AR = arm-none-eabi-ar
NM = arm-none-eabi-nm
HEX = $(OBJCOPY) -O $(FORMAT) -R .eeprom -R .fuse -R .lock -R .signature
EEP = $(OBJCOPY) -j .eeprom --set-section-flags=.eeprom="alloc,load" --change-section-lma .eeprom=0 --no-change-warnings -O $(FORMAT)
BIN =
COMMON_VPATH += $(LIB_PATH)/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include
COMMON_VPATH += $(LIB_PATH)/arm_atsam/packs/arm/cmsis/5.0.1/CMSIS/Include
COMPILEFLAGS += -funsigned-char
COMPILEFLAGS += -funsigned-bitfields
COMPILEFLAGS += -ffunction-sections
COMPILEFLAGS += -fshort-enums
COMPILEFLAGS += -fno-inline-small-functions
COMPILEFLAGS += -fno-strict-aliasing
COMPILEFLAGS += -mfloat-abi=hard
COMPILEFLAGS += -mfpu=fpv4-sp-d16
COMPILEFLAGS += -mthumb
#ALLOW_WARNINGS = yes
CFLAGS += $(COMPILEFLAGS)
CXXFLAGS += $(COMPILEFLAGS)
CXXFLAGS += -fno-exceptions -std=c++11
LDFLAGS +=-Wl,--gc-sections
LDFLAGS += -Wl,-Map="%OUT%%PROJ_NAME%.map"
LDFLAGS += -Wl,--start-group
LDFLAGS += -Wl,--end-group
LDFLAGS += --specs=rdimon.specs
LDFLAGS += -T$(LIB_PATH)/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/gcc/gcc/samd51j18a_flash.ld
OPT_DEFS += -DPROTOCOL_ARM_ATSAM
MCUFLAGS = -mcpu=$(MCU)
MCUFLAGS += -D__$(ARM_ATSAM)__
# List any extra directories to look for libraries here.
# Each directory must be seperated by a space.
# Use forward slashes for directory separators.
# For a directory that has spaces, enclose it in quotes.
EXTRALIBDIRS =
cpfirmware: warn-arm_atsam
.INTERMEDIATE: warn-arm_atsam
warn-arm_atsam: $(FIRMWARE_FORMAT)
$(info @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@)
$(info This MCU support package has a lack of support from the upstream provider (Massdrop).)
$(info There are currently questions about valid licensing, and at this stage it's likely)
$(info their boards and supporting code will be removed from QMK in the near future. Please)
$(info contact Massdrop for support, and encourage them to align their future board design)
$(info choices to gain proper license compatibility with QMK.)
$(info @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@)
# Convert hex to bin.
bin: $(BUILD_DIR)/$(TARGET).hex
$(OBJCOPY) -Iihex -Obinary $(BUILD_DIR)/$(TARGET).hex $(BUILD_DIR)/$(TARGET).bin
$(COPY) $(BUILD_DIR)/$(TARGET).bin $(TARGET).bin;

18
platforms/arm_atsam/platform_deps.h Normal file
View File

@@ -0,0 +1,18 @@
/* Copyright 2021 QMK
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#pragma once
// here just to please the build

77
platforms/arm_atsam/suspend.c Normal file
View File

@@ -0,0 +1,77 @@
#include "matrix.h"
#include "i2c_master.h"
#include "md_rgb_matrix.h"
#include "suspend.h"
/** \brief Suspend idle
*
* FIXME: needs doc
*/
void suspend_idle(uint8_t time) { /* Note: Not used anywhere currently */
}
/** \brief Run user level Power down
*
* FIXME: needs doc
*/
__attribute__((weak)) void suspend_power_down_user(void) {}
/** \brief Run keyboard level Power down
*
* FIXME: needs doc
*/
__attribute__((weak)) void suspend_power_down_kb(void) { suspend_power_down_user(); }
/** \brief Suspend power down
*
* FIXME: needs doc
*/
void suspend_power_down(void) {
#ifdef RGB_MATRIX_ENABLE
I2C3733_Control_Set(0); // Disable LED driver
#endif
suspend_power_down_kb();
}
__attribute__((weak)) void matrix_power_up(void) {}
__attribute__((weak)) void matrix_power_down(void) {}
bool suspend_wakeup_condition(void) {
matrix_power_up();
matrix_scan();
matrix_power_down();
for (uint8_t r = 0; r < MATRIX_ROWS; r++) {
if (matrix_get_row(r)) return true;
}
return false;
}
/** \brief run user level code immediately after wakeup
*
* FIXME: needs doc
*/
__attribute__((weak)) void suspend_wakeup_init_user(void) {}
/** \brief run keyboard level code immediately after wakeup
*
* FIXME: needs doc
*/
__attribute__((weak)) void suspend_wakeup_init_kb(void) { suspend_wakeup_init_user(); }
/** \brief run immediately after wakeup
*
* FIXME: needs doc
*/
void suspend_wakeup_init(void) {
#ifdef RGB_MATRIX_ENABLE
# ifdef USE_MASSDROP_CONFIGURATOR
if (led_enabled) {
I2C3733_Control_Set(1);
}
# else
I2C3733_Control_Set(1);
# endif
#endif
suspend_wakeup_init_kb();
}

19
platforms/arm_atsam/timer.c Normal file
View File

@@ -0,0 +1,19 @@
#include "samd51j18a.h"
#include "timer.h"
#include "tmk_core/protocol/arm_atsam/clks.h"
void set_time(uint64_t tset) { ms_clk = tset; }
void timer_init(void) { timer_clear(); }
uint16_t timer_read(void) { return (uint16_t)ms_clk; }
uint32_t timer_read32(void) { return (uint32_t)ms_clk; }
uint64_t timer_read64(void) { return ms_clk; }
uint16_t timer_elapsed(uint16_t tlast) { return TIMER_DIFF_16(timer_read(), tlast); }
uint32_t timer_elapsed32(uint32_t tlast) { return TIMER_DIFF_32(timer_read32(), tlast); }
void timer_clear(void) { set_time(0); }

32
platforms/atomic_util.h Normal file
View File

@@ -0,0 +1,32 @@
/* Copyright 2021 QMK
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#pragma once
// Macro to help make GPIO and other controls atomic.
#ifndef IGNORE_ATOMIC_BLOCK
# if __has_include_next("atomic_util.h")
# include_next "atomic_util.h" /* Include the platforms atomic.h */
# else
# define ATOMIC_BLOCK _Static_assert(0, "ATOMIC_BLOCK not implemented")
# define ATOMIC_BLOCK_RESTORESTATE _Static_assert(0, "ATOMIC_BLOCK_RESTORESTATE not implemented")
# define ATOMIC_BLOCK_FORCEON _Static_assert(0, "ATOMIC_BLOCK_FORCEON not implemented")
# endif
#else /* do nothing atomic macro */
# define ATOMIC_BLOCK for (uint8_t __ToDo = 1; __ToDo; __ToDo = 0)
# define ATOMIC_BLOCK_RESTORESTATE ATOMIC_BLOCK
# define ATOMIC_BLOCK_FORCEON ATOMIC_BLOCK
#endif

33
platforms/avr/_print.h Normal file
View File

@@ -0,0 +1,33 @@
/* Copyright 2012 Jun Wako <wakojun@gmail.com> */
/* Very basic print functions, intended to be used with usb_debug_only.c
* http://www.pjrc.com/teensy/
* Copyright (c) 2008 PJRC.COM, LLC
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
#pragma once
#include "avr/xprintf.h"
// Create user & normal print defines
#define print(s) xputs(PSTR(s))
#define println(s) xputs(PSTR(s "\r\n"))
#define uprint(s) xputs(PSTR(s))
#define uprintln(s) xputs(PSTR(s "\r\n"))
#define uprintf(fmt, ...) __xprintf(PSTR(fmt), ##__VA_ARGS__)

19
platforms/avr/_timer.h Normal file
View File

@@ -0,0 +1,19 @@
/* Copyright 2021 Simon Arlott
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#pragma once
// The platform is 8-bit, so prefer 16-bit timers to reduce code size
#define FAST_TIMER_T_SIZE 16

49
platforms/avr/_wait.h Normal file
View File

@@ -0,0 +1,49 @@
/* Copyright 2021 QMK
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#pragma once
#include <util/delay.h>
#define wait_ms(ms) \
do { \
if (__builtin_constant_p(ms)) { \
_delay_ms(ms); \
} else { \
for (uint16_t i = ms; i > 0; i--) { \
_delay_ms(1); \
} \
} \
} while (0)
#define wait_us(us) \
do { \
if (__builtin_constant_p(us)) { \
_delay_us(us); \
} else { \
for (uint16_t i = us; i > 0; i--) { \
_delay_us(1); \
} \
} \
} while (0)
#define wait_cpuclock(n) __builtin_avr_delay_cycles(n)
#define CPU_CLOCK F_CPU
/* The AVR series GPIOs have a one clock read delay for changes in the digital input signal.
* But here's more margin to make it two clocks. */
#ifndef GPIO_INPUT_PIN_DELAY
# define GPIO_INPUT_PIN_DELAY 2
#endif
#define waitInputPinDelay() wait_cpuclock(GPIO_INPUT_PIN_DELAY)

22
platforms/avr/atomic_util.h Normal file
View File

@@ -0,0 +1,22 @@
/* Copyright 2021 QMK
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#pragma once
/* atomic macro for AVR */
#include <util/atomic.h>
#define ATOMIC_BLOCK_RESTORESTATE ATOMIC_BLOCK(ATOMIC_RESTORESTATE)
#define ATOMIC_BLOCK_FORCEON ATOMIC_BLOCK(ATOMIC_FORCEON)

293
platforms/avr/bootloader.c Normal file
View File

@@ -0,0 +1,293 @@
#include <stdint.h>
#include <stdbool.h>
#include <avr/io.h>
#include <avr/eeprom.h>
#include <avr/interrupt.h>
#include <avr/wdt.h>
#include <util/delay.h>
#include "bootloader.h"
#include <avr/boot.h>
#ifdef PROTOCOL_LUFA
# include <LUFA/Drivers/USB/USB.h>
#endif
/** \brief Bootloader Size in *bytes*
*
* AVR Boot section size are defined by setting BOOTSZ fuse in fact. Consult with your MCU datasheet.
* Note that 'Word'(2 bytes) size and address are used in datasheet while TMK uses 'Byte'.
*
* Size of Bootloaders in bytes:
* Atmel DFU loader(ATmega32U4) 4096
* Atmel DFU loader(AT90USB128) 8192
* LUFA bootloader(ATmega32U4) 4096
* Arduino Caterina(ATmega32U4) 4096
* USBaspLoader(ATmega***) 2048
* Teensy halfKay(ATmega32U4) 512
* Teensy++ halfKay(AT90USB128) 1024
*
* AVR Boot section is located at the end of Flash memory like the followings.
*
* byte Atmel/LUFA(ATMega32u4) byte Atmel(AT90SUB128)
* 0x0000 +---------------+ 0x00000 +---------------+
* | | | |
* | | | |
* | Application | | Application |
* | | | |
* = = = =
* | | 32KB-4KB | | 128KB-8KB
* 0x7000 +---------------+ 0x1E000 +---------------+
* | Bootloader | 4KB | Bootloader | 8KB
* 0x7FFF +---------------+ 0x1FFFF +---------------+
*
*
* byte Teensy(ATMega32u4) byte Teensy++(AT90SUB128)
* 0x0000 +---------------+ 0x00000 +---------------+
* | | | |
* | | | |
* | Application | | Application |
* | | | |
* = = = =
* | | 32KB-512B | | 128KB-1KB
* 0x7E00 +---------------+ 0x1FC00 +---------------+
* | Bootloader | 512B | Bootloader | 1KB
* 0x7FFF +---------------+ 0x1FFFF +---------------+
*/
#define FLASH_SIZE (FLASHEND + 1L)
#if !defined(BOOTLOADER_SIZE)
uint16_t bootloader_start;
#endif
// compatibility between ATMega8 and ATMega88
#if !defined(MCUCSR)
# if defined(MCUSR)
# define MCUCSR MCUSR
# endif
#endif
/** \brief Entering the Bootloader via Software
*
* http://www.fourwalledcubicle.com/files/LUFA/Doc/120730/html/_page__software_bootloader_start.html
*/
#define BOOTLOADER_RESET_KEY 0xB007B007
uint32_t reset_key __attribute__((section(".noinit,\"aw\",@nobits;")));
/** \brief initialize MCU status by watchdog reset
*
* FIXME: needs doc
*/
__attribute__((weak)) void bootloader_jump(void) {
#if !defined(BOOTLOADER_SIZE)
uint8_t high_fuse = boot_lock_fuse_bits_get(GET_HIGH_FUSE_BITS);
if (high_fuse & ~(FUSE_BOOTSZ0 & FUSE_BOOTSZ1)) {
bootloader_start = (FLASH_SIZE - 512) >> 1;
} else if (high_fuse & ~(FUSE_BOOTSZ1)) {
bootloader_start = (FLASH_SIZE - 1024) >> 1;
} else if (high_fuse & ~(FUSE_BOOTSZ0)) {
bootloader_start = (FLASH_SIZE - 2048) >> 1;
} else {
bootloader_start = (FLASH_SIZE - 4096) >> 1;
}
#endif
// Something like this might work, but it compiled larger than the block above
// bootloader_start = FLASH_SIZE - (256 << (~high_fuse & 0b110 >> 1));
#if defined(BOOTLOADER_HALFKAY)
// http://www.pjrc.com/teensy/jump_to_bootloader.html
cli();
// disable watchdog, if enabled (it's not)
// disable all peripherals
// a shutdown call might make sense here
UDCON = 1;
USBCON = (1 << FRZCLK); // disable USB
UCSR1B = 0;
_delay_ms(5);
# if defined(__AVR_AT90USB162__) // Teensy 1.0
EIMSK = 0;
PCICR = 0;
SPCR = 0;
ACSR = 0;
EECR = 0;
TIMSK0 = 0;
TIMSK1 = 0;
UCSR1B = 0;
DDRB = 0;
DDRC = 0;
DDRD = 0;
PORTB = 0;
PORTC = 0;
PORTD = 0;
asm volatile("jmp 0x3E00");
# elif defined(__AVR_ATmega32U4__) // Teensy 2.0
EIMSK = 0;
PCICR = 0;
SPCR = 0;
ACSR = 0;
EECR = 0;
ADCSRA = 0;
TIMSK0 = 0;
TIMSK1 = 0;
TIMSK3 = 0;
TIMSK4 = 0;
UCSR1B = 0;
TWCR = 0;
DDRB = 0;
DDRC = 0;
DDRD = 0;
DDRE = 0;
DDRF = 0;
TWCR = 0;
PORTB = 0;
PORTC = 0;
PORTD = 0;
PORTE = 0;
PORTF = 0;
asm volatile("jmp 0x7E00");
# elif defined(__AVR_AT90USB646__) // Teensy++ 1.0
EIMSK = 0;
PCICR = 0;
SPCR = 0;
ACSR = 0;
EECR = 0;
ADCSRA = 0;
TIMSK0 = 0;
TIMSK1 = 0;
TIMSK2 = 0;
TIMSK3 = 0;
UCSR1B = 0;
TWCR = 0;
DDRA = 0;
DDRB = 0;
DDRC = 0;
DDRD = 0;
DDRE = 0;
DDRF = 0;
PORTA = 0;
PORTB = 0;
PORTC = 0;
PORTD = 0;
PORTE = 0;
PORTF = 0;
asm volatile("jmp 0xFC00");
# elif defined(__AVR_AT90USB1286__) // Teensy++ 2.0
EIMSK = 0;
PCICR = 0;
SPCR = 0;
ACSR = 0;
EECR = 0;
ADCSRA = 0;
TIMSK0 = 0;
TIMSK1 = 0;
TIMSK2 = 0;
TIMSK3 = 0;
UCSR1B = 0;
TWCR = 0;
DDRA = 0;
DDRB = 0;
DDRC = 0;
DDRD = 0;
DDRE = 0;
DDRF = 0;
PORTA = 0;
PORTB = 0;
PORTC = 0;
PORTD = 0;
PORTE = 0;
PORTF = 0;
asm volatile("jmp 0x1FC00");
# endif
#elif defined(BOOTLOADER_CATERINA)
// this block may be optional
// TODO: figure it out
uint16_t *const bootKeyPtr = (uint16_t *)0x0800;
// Value used by Caterina bootloader use to determine whether to run the
// sketch or the bootloader programmer.
uint16_t bootKey = 0x7777;
*bootKeyPtr = bootKey;
// setup watchdog timeout
wdt_enable(WDTO_60MS);
while (1) {
} // wait for watchdog timer to trigger
#elif defined(BOOTLOADER_USBASP)
// Taken with permission of Stephan Baerwolf from https://github.com/tinyusbboard/API/blob/master/apipage.c
wdt_enable(WDTO_15MS);
wdt_reset();
asm volatile("cli \n\t"
"ldi r29 , %[ramendhi] \n\t"
"ldi r28 , %[ramendlo] \n\t"
# if (FLASHEND > 131071)
"ldi r18 , %[bootaddrhi] \n\t"
"st Y+, r18 \n\t"
# endif
"ldi r18 , %[bootaddrme] \n\t"
"st Y+, r18 \n\t"
"ldi r18 , %[bootaddrlo] \n\t"
"st Y+, r18 \n\t"
"out %[mcucsrio], __zero_reg__ \n\t"
"bootloader_startup_loop%=: \n\t"
"rjmp bootloader_startup_loop%= \n\t"
:
: [mcucsrio] "I"(_SFR_IO_ADDR(MCUCSR)),
# if (FLASHEND > 131071)
[ramendhi] "M"(((RAMEND - 2) >> 8) & 0xff), [ramendlo] "M"(((RAMEND - 2) >> 0) & 0xff), [bootaddrhi] "M"((((FLASH_SIZE - BOOTLOADER_SIZE) >> 1) >> 16) & 0xff),
# else
[ramendhi] "M"(((RAMEND - 1) >> 8) & 0xff), [ramendlo] "M"(((RAMEND - 1) >> 0) & 0xff),
# endif
[bootaddrme] "M"((((FLASH_SIZE - BOOTLOADER_SIZE) >> 1) >> 8) & 0xff), [bootaddrlo] "M"((((FLASH_SIZE - BOOTLOADER_SIZE) >> 1) >> 0) & 0xff));
#else // Assume remaining boards are DFU, even if the flag isn't set
# if !(defined(__AVR_ATmega32A__) || defined(__AVR_ATmega328P__) || defined(__AVR_ATmega328__) || defined(__AVR_ATtiny85__)) // no USB - maybe BOOTLOADER_BOOTLOADHID instead though?
UDCON = 1;
USBCON = (1 << FRZCLK); // disable USB
UCSR1B = 0;
_delay_ms(5); // 5 seems to work fine
# endif
# ifdef BOOTLOADER_BOOTLOADHID
// force bootloadHID to stay in bootloader mode, so that it waits
// for a new firmware to be flashed
eeprom_write_byte((uint8_t *)1, 0x00);
# endif
// watchdog reset
reset_key = BOOTLOADER_RESET_KEY;
wdt_enable(WDTO_250MS);
for (;;)
;
#endif
}
/* this runs before main() */
void bootloader_jump_after_watchdog_reset(void) __attribute__((used, naked, section(".init3")));
void bootloader_jump_after_watchdog_reset(void) {
#ifndef BOOTLOADER_HALFKAY
if ((MCUCSR & (1 << WDRF)) && reset_key == BOOTLOADER_RESET_KEY) {
reset_key = 0;
// My custom USBasploader requires this to come up.
MCUCSR = 0;
// Seems like Teensy halfkay loader requires clearing WDRF and disabling watchdog.
MCUCSR &= ~(1 << WDRF);
wdt_disable();
// This is compled into 'icall', address should be in word unit, not byte.
# ifdef BOOTLOADER_SIZE
((void (*)(void))((FLASH_SIZE - BOOTLOADER_SIZE) >> 1))();
# else
asm("ijmp" ::"z"(bootloader_start));
# endif
}
#endif
}

21
platforms/avr/bootloader_size.c Normal file
View File

@@ -0,0 +1,21 @@
// Copyright 2017 Jack Humbert
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
#include <avr/io.h>
#include <avr/boot.h>
// clang-format off
// this is not valid C - it's for computing the size available on the chip
AVR_SIZE: FLASHEND + 1 - BOOTLOADER_SIZE

23
platforms/avr/drivers/analog.c
View File

@@ -23,29 +23,6 @@ static uint8_t aref = ADC_REF_POWER;
void analogReference(uint8_t mode) { aref = mode & (_BV(REFS1) | _BV(REFS0)); }
// Arduino compatible pin input
int16_t analogRead(uint8_t pin) {
#if defined(__AVR_ATmega32U4__)
// clang-format off
static const uint8_t PROGMEM pin_to_mux[] = {
//A0 A1 A2 A3 A4 A5
//F7 F6 F5 F4 F1 F0
0x07, 0x06, 0x05, 0x04, 0x01, 0x00,
//A6 A7 A8 A9 A10 A11
//D4 D7 B4 B5 B6 D6
0x20, 0x22, 0x23, 0x24, 0x25, 0x21
};
// clang-format on
if (pin >= 12) return 0;
return adc_read(pgm_read_byte(pin_to_mux + pin));
#elif defined(__AVR_AT90USB646__) || defined(__AVR_AT90USB647__) || defined(__AVR_AT90USB1286__) || defined(__AVR_AT90USB1287__) || defined(__AVR_ATmega328P__) || defined(__AVR_ATmega328__)
if (pin >= 8) return 0;
return adc_read(pin);
#else
return 0;
#endif
}
int16_t analogReadPin(pin_t pin) { return adc_read(pinToMux(pin)); }
uint8_t pinToMux(pin_t pin) {

3
platforms/avr/drivers/analog.h
View File

@@ -22,8 +22,7 @@
#ifdef __cplusplus
extern "C" {
#endif
void analogReference(uint8_t mode);
int16_t analogRead(uint8_t pin);
void analogReference(uint8_t mode);
int16_t analogReadPin(pin_t pin);
uint8_t pinToMux(pin_t pin);

17
platforms/avr/drivers/audio_pwm.h Normal file
View File

@@ -0,0 +1,17 @@
/* Copyright 2020 Jack Humbert
* Copyright 2020 JohSchneider
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#pragma once

332
platforms/avr/drivers/audio_pwm_hardware.c Normal file
View File

@@ -0,0 +1,332 @@
/* Copyright 2016 Jack Humbert
* Copyright 2020 JohSchneider
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#if defined(__AVR__)
# include <avr/pgmspace.h>
# include <avr/interrupt.h>
# include <avr/io.h>
#endif
#include "audio.h"
extern bool playing_note;
extern bool playing_melody;
extern uint8_t note_timbre;
#define CPU_PRESCALER 8
/*
Audio Driver: PWM
drive up to two speakers through the AVR PWM hardware-peripheral, using timer1 and/or timer3 on Atmega32U4.
the primary channel_1 can be connected to either pin PC4 PC5 or PC6 (the later being used by most AVR based keyboards) with a PMW signal generated by timer3
and an optional secondary channel_2 on either pin PB5, PB6 or PB7, with a PWM signal from timer1
alternatively, the PWM pins on PORTB can be used as only/primary speaker
*/
#if defined(AUDIO_PIN) && (AUDIO_PIN != C4) && (AUDIO_PIN != C5) && (AUDIO_PIN != C6) && (AUDIO_PIN != B5) && (AUDIO_PIN != B6) && (AUDIO_PIN != B7) && (AUDIO_PIN != D5)
# error "Audio feature enabled, but no suitable pin selected as AUDIO_PIN - see docs/feature_audio under the AVR settings for available options."
#endif
#if (AUDIO_PIN == C4) || (AUDIO_PIN == C5) || (AUDIO_PIN == C6)
# define AUDIO1_PIN_SET
# define AUDIO1_TIMSKx TIMSK3
# define AUDIO1_TCCRxA TCCR3A
# define AUDIO1_TCCRxB TCCR3B
# define AUDIO1_ICRx ICR3
# define AUDIO1_WGMx0 WGM30
# define AUDIO1_WGMx1 WGM31
# define AUDIO1_WGMx2 WGM32
# define AUDIO1_WGMx3 WGM33
# define AUDIO1_CSx0 CS30
# define AUDIO1_CSx1 CS31
# define AUDIO1_CSx2 CS32
# if (AUDIO_PIN == C6)
# define AUDIO1_COMxy0 COM3A0
# define AUDIO1_COMxy1 COM3A1
# define AUDIO1_OCIExy OCIE3A
# define AUDIO1_OCRxy OCR3A
# define AUDIO1_PIN C6
# define AUDIO1_TIMERx_COMPy_vect TIMER3_COMPA_vect
# elif (AUDIO_PIN == C5)
# define AUDIO1_COMxy0 COM3B0
# define AUDIO1_COMxy1 COM3B1
# define AUDIO1_OCIExy OCIE3B
# define AUDIO1_OCRxy OCR3B
# define AUDIO1_PIN C5
# define AUDIO1_TIMERx_COMPy_vect TIMER3_COMPB_vect
# elif (AUDIO_PIN == C4)
# define AUDIO1_COMxy0 COM3C0
# define AUDIO1_COMxy1 COM3C1
# define AUDIO1_OCIExy OCIE3C
# define AUDIO1_OCRxy OCR3C
# define AUDIO1_PIN C4
# define AUDIO1_TIMERx_COMPy_vect TIMER3_COMPC_vect
# endif
#endif
#if defined(AUDIO_PIN) && defined(AUDIO_PIN_ALT) && (AUDIO_PIN == AUDIO_PIN_ALT)
# error "Audio feature: AUDIO_PIN and AUDIO_PIN_ALT on the same pin makes no sense."
#endif
#if ((AUDIO_PIN == B5) && ((AUDIO_PIN_ALT == B6) || (AUDIO_PIN_ALT == B7))) || ((AUDIO_PIN == B6) && ((AUDIO_PIN_ALT == B5) || (AUDIO_PIN_ALT == B7))) || ((AUDIO_PIN == B7) && ((AUDIO_PIN_ALT == B5) || (AUDIO_PIN_ALT == B6)))
# error "Audio feature: PORTB as AUDIO_PIN and AUDIO_PIN_ALT at the same time is not supported."
#endif
#if defined(AUDIO_PIN_ALT) && (AUDIO_PIN_ALT != B5) && (AUDIO_PIN_ALT != B6) && (AUDIO_PIN_ALT != B7)
# error "Audio feature: the pin selected as AUDIO_PIN_ALT is not supported."
#endif
#if (AUDIO_PIN == B5) || (AUDIO_PIN == B6) || (AUDIO_PIN == B7) || (AUDIO_PIN_ALT == B5) || (AUDIO_PIN_ALT == B6) || (AUDIO_PIN_ALT == B7) || (AUDIO_PIN == D5)
# define AUDIO2_PIN_SET
# define AUDIO2_TIMSKx TIMSK1
# define AUDIO2_TCCRxA TCCR1A
# define AUDIO2_TCCRxB TCCR1B
# define AUDIO2_ICRx ICR1
# define AUDIO2_WGMx0 WGM10
# define AUDIO2_WGMx1 WGM11
# define AUDIO2_WGMx2 WGM12
# define AUDIO2_WGMx3 WGM13
# define AUDIO2_CSx0 CS10
# define AUDIO2_CSx1 CS11
# define AUDIO2_CSx2 CS12
# if (AUDIO_PIN == B5) || (AUDIO_PIN_ALT == B5)
# define AUDIO2_COMxy0 COM1A0
# define AUDIO2_COMxy1 COM1A1
# define AUDIO2_OCIExy OCIE1A
# define AUDIO2_OCRxy OCR1A
# define AUDIO2_PIN B5
# define AUDIO2_TIMERx_COMPy_vect TIMER1_COMPA_vect
# elif (AUDIO_PIN == B6) || (AUDIO_PIN_ALT == B6)
# define AUDIO2_COMxy0 COM1B0
# define AUDIO2_COMxy1 COM1B1
# define AUDIO2_OCIExy OCIE1B
# define AUDIO2_OCRxy OCR1B
# define AUDIO2_PIN B6
# define AUDIO2_TIMERx_COMPy_vect TIMER1_COMPB_vect
# elif (AUDIO_PIN == B7) || (AUDIO_PIN_ALT == B7)
# define AUDIO2_COMxy0 COM1C0
# define AUDIO2_COMxy1 COM1C1
# define AUDIO2_OCIExy OCIE1C
# define AUDIO2_OCRxy OCR1C
# define AUDIO2_PIN B7
# define AUDIO2_TIMERx_COMPy_vect TIMER1_COMPC_vect
# elif (AUDIO_PIN == D5) && defined(__AVR_ATmega32A__)
# pragma message "Audio support for ATmega32A is experimental and can cause crashes."
# undef AUDIO2_TIMSKx
# define AUDIO2_TIMSKx TIMSK
# define AUDIO2_COMxy0 COM1A0
# define AUDIO2_COMxy1 COM1A1
# define AUDIO2_OCIExy OCIE1A
# define AUDIO2_OCRxy OCR1A
# define AUDIO2_PIN D5
# define AUDIO2_TIMERx_COMPy_vect TIMER1_COMPA_vect
# endif
#endif
// C6 seems to be the assumed default by many existing keyboard - but sill warn the user
#if !defined(AUDIO1_PIN_SET) && !defined(AUDIO2_PIN_SET)
# pragma message "Audio feature enabled, but no suitable pin selected - see docs/feature_audio under the AVR settings for available options. Don't expect to hear anything... :-)"
// TODO: make this an error - go through the breaking-change-process and change all keyboards to the new define
#endif
// -----------------------------------------------------------------------------
#ifdef AUDIO1_PIN_SET
static float channel_1_frequency = 0.0f;
void channel_1_set_frequency(float freq) {
if (freq == 0.0f) // a pause/rest is a valid "note" with freq=0
{
// disable the output, but keep the pwm-ISR going (with the previous
// frequency) so the audio-state keeps getting updated
// Note: setting the duty-cycle 0 is not possible on non-inverting PWM mode - see the AVR data-sheet
AUDIO1_TCCRxA &= ~(_BV(AUDIO1_COMxy1) | _BV(AUDIO1_COMxy0));
return;
} else {
AUDIO1_TCCRxA |= _BV(AUDIO1_COMxy1); // enable output, PWM mode
}
channel_1_frequency = freq;
// set pwm period
AUDIO1_ICRx = (uint16_t)(((float)F_CPU) / (freq * CPU_PRESCALER));
// and duty cycle
AUDIO1_OCRxy = (uint16_t)((((float)F_CPU) / (freq * CPU_PRESCALER)) * note_timbre / 100);
}
void channel_1_start(void) {
// enable timer-counter ISR
AUDIO1_TIMSKx |= _BV(AUDIO1_OCIExy);
// enable timer-counter output
AUDIO1_TCCRxA |= _BV(AUDIO1_COMxy1);
}
void channel_1_stop(void) {
// disable timer-counter ISR
AUDIO1_TIMSKx &= ~_BV(AUDIO1_OCIExy);
// disable timer-counter output
AUDIO1_TCCRxA &= ~(_BV(AUDIO1_COMxy1) | _BV(AUDIO1_COMxy0));
}
#endif
#ifdef AUDIO2_PIN_SET
static float channel_2_frequency = 0.0f;
void channel_2_set_frequency(float freq) {
if (freq == 0.0f) {
AUDIO2_TCCRxA &= ~(_BV(AUDIO2_COMxy1) | _BV(AUDIO2_COMxy0));
return;
} else {
AUDIO2_TCCRxA |= _BV(AUDIO2_COMxy1);
}
channel_2_frequency = freq;
AUDIO2_ICRx = (uint16_t)(((float)F_CPU) / (freq * CPU_PRESCALER));
AUDIO2_OCRxy = (uint16_t)((((float)F_CPU) / (freq * CPU_PRESCALER)) * note_timbre / 100);
}
float channel_2_get_frequency(void) { return channel_2_frequency; }
void channel_2_start(void) {
AUDIO2_TIMSKx |= _BV(AUDIO2_OCIExy);
AUDIO2_TCCRxA |= _BV(AUDIO2_COMxy1);
}
void channel_2_stop(void) {
AUDIO2_TIMSKx &= ~_BV(AUDIO2_OCIExy);
AUDIO2_TCCRxA &= ~(_BV(AUDIO2_COMxy1) | _BV(AUDIO2_COMxy0));
}
#endif
void audio_driver_initialize() {
#ifdef AUDIO1_PIN_SET
channel_1_stop();
setPinOutput(AUDIO1_PIN);
#endif
#ifdef AUDIO2_PIN_SET
channel_2_stop();
setPinOutput(AUDIO2_PIN);
#endif
// TCCR3A / TCCR3B: Timer/Counter #3 Control Registers TCCR3A/TCCR3B, TCCR1A/TCCR1B
// Compare Output Mode (COM3An and COM1An) = 0b00 = Normal port operation
// OC3A -- PC6
// OC3B -- PC5
// OC3C -- PC4
// OC1A -- PB5
// OC1B -- PB6
// OC1C -- PB7
// Waveform Generation Mode (WGM3n) = 0b1110 = Fast PWM Mode 14. Period = ICR3, Duty Cycle OCR3A)
// OCR3A - PC6
// OCR3B - PC5
// OCR3C - PC4
// OCR1A - PB5
// OCR1B - PB6
// OCR1C - PB7
// Clock Select (CS3n) = 0b010 = Clock / 8
#ifdef AUDIO1_PIN_SET
// initialize timer-counter
AUDIO1_TCCRxA = (0 << AUDIO1_COMxy1) | (0 << AUDIO1_COMxy0) | (1 << AUDIO1_WGMx1) | (0 << AUDIO1_WGMx0);
AUDIO1_TCCRxB = (1 << AUDIO1_WGMx3) | (1 << AUDIO1_WGMx2) | (0 << AUDIO1_CSx2) | (1 << AUDIO1_CSx1) | (0 << AUDIO1_CSx0);
#endif
#ifdef AUDIO2_PIN_SET
AUDIO2_TCCRxA = (0 << AUDIO2_COMxy1) | (0 << AUDIO2_COMxy0) | (1 << AUDIO2_WGMx1) | (0 << AUDIO2_WGMx0);
AUDIO2_TCCRxB = (1 << AUDIO2_WGMx3) | (1 << AUDIO2_WGMx2) | (0 << AUDIO2_CSx2) | (1 << AUDIO2_CSx1) | (0 << AUDIO2_CSx0);
#endif
}
void audio_driver_stop() {
#ifdef AUDIO1_PIN_SET
channel_1_stop();
#endif
#ifdef AUDIO2_PIN_SET
channel_2_stop();
#endif
}
void audio_driver_start(void) {
#ifdef AUDIO1_PIN_SET
channel_1_start();
if (playing_note) {
channel_1_set_frequency(audio_get_processed_frequency(0));
}
#endif
#if !defined(AUDIO1_PIN_SET) && defined(AUDIO2_PIN_SET)
channel_2_start();
if (playing_note) {
channel_2_set_frequency(audio_get_processed_frequency(0));
}
#endif
}
static volatile uint32_t isr_counter = 0;
#ifdef AUDIO1_PIN_SET
ISR(AUDIO1_TIMERx_COMPy_vect) {
isr_counter++;
if (isr_counter < channel_1_frequency / (CPU_PRESCALER * 8)) return;
isr_counter = 0;
bool state_changed = audio_update_state();
if (!playing_note && !playing_melody) {
channel_1_stop();
# ifdef AUDIO2_PIN_SET
channel_2_stop();
# endif
return;
}
if (state_changed) {
channel_1_set_frequency(audio_get_processed_frequency(0));
# ifdef AUDIO2_PIN_SET
if (audio_get_number_of_active_tones() > 1) {
channel_2_set_frequency(audio_get_processed_frequency(1));
} else {
channel_2_stop();
}
# endif
}
}
#endif
#if !defined(AUDIO1_PIN_SET) && defined(AUDIO2_PIN_SET)
ISR(AUDIO2_TIMERx_COMPy_vect) {
isr_counter++;
if (isr_counter < channel_2_frequency / (CPU_PRESCALER * 8)) return;
isr_counter = 0;
bool state_changed = audio_update_state();
if (!playing_note && !playing_melody) {
channel_2_stop();
return;
}
if (state_changed) {
channel_2_set_frequency(audio_get_processed_frequency(0));
}
}
#endif

56
platforms/avr/drivers/i2c_master.c
View File

@@ -202,6 +202,25 @@ i2c_status_t i2c_writeReg(uint8_t devaddr, uint8_t regaddr, const uint8_t* data,
return status;
}
i2c_status_t i2c_writeReg16(uint8_t devaddr, uint16_t regaddr, const uint8_t* data, uint16_t length, uint16_t timeout) {
i2c_status_t status = i2c_start(devaddr | 0x00, timeout);
if (status >= 0) {
status = i2c_write(regaddr >> 8, timeout);
if (status >= 0) {
status = i2c_write(regaddr & 0xFF, timeout);
for (uint16_t i = 0; i < length && status >= 0; i++) {
status = i2c_write(data[i], timeout);
}
}
}
i2c_stop();
return status;
}
i2c_status_t i2c_readReg(uint8_t devaddr, uint8_t regaddr, uint8_t* data, uint16_t length, uint16_t timeout) {
i2c_status_t status = i2c_start(devaddr, timeout);
if (status < 0) {
@@ -235,6 +254,43 @@ error:
return (status < 0) ? status : I2C_STATUS_SUCCESS;
}
i2c_status_t i2c_readReg16(uint8_t devaddr, uint16_t regaddr, uint8_t* data, uint16_t length, uint16_t timeout) {
i2c_status_t status = i2c_start(devaddr, timeout);
if (status < 0) {
goto error;
}
status = i2c_write(regaddr >> 8, timeout);
if (status < 0) {
goto error;
}
status = i2c_write(regaddr & 0xFF, timeout);
if (status < 0) {
goto error;
}
status = i2c_start(devaddr | 0x01, timeout);
for (uint16_t i = 0; i < (length - 1) && status >= 0; i++) {
status = i2c_read_ack(timeout);
if (status >= 0) {
data[i] = status;
}
}
if (status >= 0) {
status = i2c_read_nack(timeout);
if (status >= 0) {
data[(length - 1)] = status;
}
}
error:
i2c_stop();
return (status < 0) ? status : I2C_STATUS_SUCCESS;
}
void i2c_stop(void) {
// transmit STOP condition
TWCR = (1 << TWINT) | (1 << TWEN) | (1 << TWSTO);

2
platforms/avr/drivers/i2c_master.h
View File

@@ -39,5 +39,7 @@ int16_t i2c_read_nack(uint16_t timeout);
i2c_status_t i2c_transmit(uint8_t address, const uint8_t* data, uint16_t length, uint16_t timeout);
i2c_status_t i2c_receive(uint8_t address, uint8_t* data, uint16_t length, uint16_t timeout);
i2c_status_t i2c_writeReg(uint8_t devaddr, uint8_t regaddr, const uint8_t* data, uint16_t length, uint16_t timeout);
i2c_status_t i2c_writeReg16(uint8_t devaddr, uint16_t regaddr, const uint8_t* data, uint16_t length, uint16_t timeout);
i2c_status_t i2c_readReg(uint8_t devaddr, uint8_t regaddr, uint8_t* data, uint16_t length, uint16_t timeout);
i2c_status_t i2c_readReg16(uint8_t devaddr, uint16_t regaddr, uint8_t* data, uint16_t length, uint16_t timeout);
void i2c_stop(void);

51
platforms/avr/drivers/ps2/ps2_io.c Normal file
View File

@@ -0,0 +1,51 @@
#include <stdbool.h>
#include "ps2_io.h"
#include "gpio.h"
#include "wait.h"
/* Check port settings for clock and data line */
#if !(defined(PS2_CLOCK_PIN))
# error "PS/2 clock setting is required in config.h"
#endif
#if !(defined(PS2_DATA_PIN))
# error "PS/2 data setting is required in config.h"
#endif
/*
* Clock
*/
void clock_init(void) {}
void clock_lo(void) {
// Transition from input with pull-up to output low via Hi-Z instead of output high
writePinLow(PS2_CLOCK_PIN);
setPinOutput(PS2_CLOCK_PIN);
}
void clock_hi(void) { setPinInputHigh(PS2_CLOCK_PIN); }
bool clock_in(void) {
setPinInputHigh(PS2_CLOCK_PIN);
wait_us(1);
return readPin(PS2_CLOCK_PIN);
}
/*
* Data
*/
void data_init(void) {}
void data_lo(void) {
// Transition from input with pull-up to output low via Hi-Z instead of output high
writePinLow(PS2_DATA_PIN);
setPinOutput(PS2_DATA_PIN);
}
void data_hi(void) { setPinInputHigh(PS2_DATA_PIN); }
bool data_in(void) {
setPinInputHigh(PS2_DATA_PIN);
wait_us(1);
return readPin(PS2_DATA_PIN);
}

227
platforms/avr/drivers/ps2/ps2_usart.c Normal file
View File

@@ -0,0 +1,227 @@
/*
Copyright 2010,2011,2012,2013 Jun WAKO <wakojun@gmail.com>
This software is licensed with a Modified BSD License.
All of this is supposed to be Free Software, Open Source, DFSG-free,
GPL-compatible, and OK to use in both free and proprietary applications.
Additions and corrections to this file are welcome.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in
the documentation and/or other materials provided with the
distribution.
* Neither the name of the copyright holders nor the names of
contributors may be used to endorse or promote products derived
from this software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
*/
/*
* PS/2 protocol USART version
*/
#include <stdbool.h>
#include <avr/interrupt.h>
#include <util/delay.h>
#include "gpio.h"
#include "ps2.h"
#include "ps2_io.h"
#include "print.h"
#ifndef PS2_CLOCK_DDR
# define PS2_CLOCK_DDR PORTx_ADDRESS(PS2_CLOCK_PIN)
#endif
#ifndef PS2_CLOCK_BIT
# define PS2_CLOCK_BIT (PS2_CLOCK_PIN & 0xF)
#endif
#ifndef PS2_DATA_DDR
# define PS2_DATA_DDR PORTx_ADDRESS(PS2_DATA_PIN)
#endif
#ifndef PS2_DATA_BIT
# define PS2_DATA_BIT (PS2_DATA_PIN & 0xF)
#endif
#define WAIT(stat, us, err) \
do { \
if (!wait_##stat(us)) { \
ps2_error = err; \
goto ERROR; \
} \
} while (0)
uint8_t ps2_error = PS2_ERR_NONE;
static inline uint8_t pbuf_dequeue(void);
static inline void pbuf_enqueue(uint8_t data);
static inline bool pbuf_has_data(void);
static inline void pbuf_clear(void);
void ps2_host_init(void) {
idle(); // without this many USART errors occur when cable is disconnected
PS2_USART_INIT();
PS2_USART_RX_INT_ON();
// POR(150-2000ms) plus BAT(300-500ms) may take 2.5sec([3]p.20)
//_delay_ms(2500);
}
uint8_t ps2_host_send(uint8_t data) {
bool parity = true;
ps2_error = PS2_ERR_NONE;
PS2_USART_OFF();
/* terminate a transmission if we have */
inhibit();
_delay_us(100); // [4]p.13
/* 'Request to Send' and Start bit */
data_lo();
clock_hi();
WAIT(clock_lo, 10000, 10); // 10ms [5]p.50
/* Data bit[2-9] */
for (uint8_t i = 0; i < 8; i++) {
_delay_us(15);
if (data & (1 << i)) {
parity = !parity;
data_hi();
} else {
data_lo();
}
WAIT(clock_hi, 50, 2);
WAIT(clock_lo, 50, 3);
}
/* Parity bit */
_delay_us(15);
if (parity) {
data_hi();
} else {
data_lo();
}
WAIT(clock_hi, 50, 4);
WAIT(clock_lo, 50, 5);
/* Stop bit */
_delay_us(15);
data_hi();
/* Ack */
WAIT(data_lo, 50, 6);
WAIT(clock_lo, 50, 7);
/* wait for idle state */
WAIT(clock_hi, 50, 8);
WAIT(data_hi, 50, 9);
idle();
PS2_USART_INIT();
PS2_USART_RX_INT_ON();
return ps2_host_recv_response();
ERROR:
idle();
PS2_USART_INIT();
PS2_USART_RX_INT_ON();
return 0;
}
uint8_t ps2_host_recv_response(void) {
// Command may take 25ms/20ms at most([5]p.46, [3]p.21)
uint8_t retry = 25;
while (retry-- && !pbuf_has_data()) {
_delay_ms(1);
}
return pbuf_dequeue();
}
uint8_t ps2_host_recv(void) {
if (pbuf_has_data()) {
ps2_error = PS2_ERR_NONE;
return pbuf_dequeue();
} else {
ps2_error = PS2_ERR_NODATA;
return 0;
}
}
ISR(PS2_USART_RX_VECT) {
// TODO: request RESEND when error occurs?
uint8_t error = PS2_USART_ERROR; // USART error should be read before data
uint8_t data = PS2_USART_RX_DATA;
if (!error) {
pbuf_enqueue(data);
} else {
xprintf("PS2 USART error: %02X data: %02X\n", error, data);
}
}
/* send LED state to keyboard */
void ps2_host_set_led(uint8_t led) {
ps2_host_send(0xED);
ps2_host_send(led);
}
/*--------------------------------------------------------------------
* Ring buffer to store scan codes from keyboard
*------------------------------------------------------------------*/
#define PBUF_SIZE 32
static uint8_t pbuf[PBUF_SIZE];
static uint8_t pbuf_head = 0;
static uint8_t pbuf_tail = 0;
static inline void pbuf_enqueue(uint8_t data) {
uint8_t sreg = SREG;
cli();
uint8_t next = (pbuf_head + 1) % PBUF_SIZE;
if (next != pbuf_tail) {
pbuf[pbuf_head] = data;
pbuf_head = next;
} else {
print("pbuf: full\n");
}
SREG = sreg;
}
static inline uint8_t pbuf_dequeue(void) {
uint8_t val = 0;
uint8_t sreg = SREG;
cli();
if (pbuf_head != pbuf_tail) {
val = pbuf[pbuf_tail];
pbuf_tail = (pbuf_tail + 1) % PBUF_SIZE;
}
SREG = sreg;
return val;
}
static inline bool pbuf_has_data(void) {
uint8_t sreg = SREG;
cli();
bool has_data = (pbuf_head != pbuf_tail);
SREG = sreg;
return has_data;
}
static inline void pbuf_clear(void) {
uint8_t sreg = SREG;
cli();
pbuf_head = pbuf_tail = 0;
SREG = sreg;
}

26
platforms/avr/drivers/uart.c
View File

@@ -100,7 +100,7 @@ void uart_init(uint32_t baud) {
}
// Transmit a byte
void uart_putchar(uint8_t c) {
void uart_write(uint8_t data) {
uint8_t i;
i = tx_buffer_head + 1;
@@ -110,27 +110,39 @@ void uart_putchar(uint8_t c) {
while (tx_buffer_tail == i)
; // wait until space in buffer
// cli();
tx_buffer[i] = c;
tx_buffer[i] = data;
tx_buffer_head = i;
UCSRnB = (1 << RXENn) | (1 << TXENn) | (1 << RXCIEn) | (1 << UDRIEn);
// sei();
}
// Receive a byte
uint8_t uart_getchar(void) {
uint8_t c, i;
uint8_t uart_read(void) {
uint8_t data, i;
while (rx_buffer_head == rx_buffer_tail)
; // wait for character
i = rx_buffer_tail + 1;
if (i >= RX_BUFFER_SIZE) i = 0;
c = rx_buffer[i];
data = rx_buffer[i];
rx_buffer_tail = i;
return c;
return data;
}
void uart_transmit(const uint8_t *data, uint16_t length) {
for (uint16_t i = 0; i < length; i++) {
uart_write(data[i]);
}
}
void uart_receive(uint8_t *data, uint16_t length) {
for (uint16_t i = 0; i < length; i++) {
data[i] = uart_read();
}
}
// Return whether the number of bytes waiting in the receive buffer is nonzero.
// Call this before uart_getchar() to check if it will need
// Call this before uart_read() to check if it will need
// to wait for a byte to arrive.
bool uart_available(void) {
uint8_t head, tail;

8
platforms/avr/drivers/uart.h
View File

@@ -28,8 +28,12 @@
void uart_init(uint32_t baud);
void uart_putchar(uint8_t c);
void uart_write(uint8_t data);
uint8_t uart_getchar(void);
uint8_t uart_read(void);
void uart_transmit(const uint8_t *data, uint16_t length);
void uart_receive(uint8_t *data, uint16_t length);
bool uart_available(void);

11
platforms/avr/drivers/ws2812.c
View File

@@ -52,20 +52,15 @@ void ws2812_setleds(LED_TYPE *ledarray, uint16_t number_of_leds) {
using the fast 800kHz clockless WS2811/2812 protocol.
*/
// Timing in ns
#define w_zeropulse 350
#define w_onepulse 900
#define w_totalperiod 1250
// Fixed cycles used by the inner loop
#define w_fixedlow 2
#define w_fixedhigh 4
#define w_fixedtotal 8
// Insert NOPs to match the timing, if possible
#define w_zerocycles (((F_CPU / 1000) * w_zeropulse) / 1000000)
#define w_onecycles (((F_CPU / 1000) * w_onepulse + 500000) / 1000000)
#define w_totalcycles (((F_CPU / 1000) * w_totalperiod + 500000) / 1000000)
#define w_zerocycles (((F_CPU / 1000) * WS2812_T0H) / 1000000)
#define w_onecycles (((F_CPU / 1000) * WS2812_T1H + 500000) / 1000000)
#define w_totalcycles (((F_CPU / 1000) * WS2812_TIMING + 500000) / 1000000)
// w1_nops - nops between rising edge and falling edge - low
#if w_zerocycles >= w_fixedlow

9
platforms/avr/flash.mk
View File

@@ -130,6 +130,15 @@ avrdude-split-right: $(BUILD_DIR)/$(TARGET).hex check-size cpfirmware
$(call EXEC_AVRDUDE,eeprom-righthand.eep)
define EXEC_USBASP
if $(AVRDUDE_PROGRAMMER) -p $(AVRDUDE_MCU) -c usbasp 2>&1 | grep -q "could not find USB device with"; then \
printf "$(MSG_BOOTLOADER_NOT_FOUND_QUICK_RETRY)" ;\
sleep $(BOOTLOADER_RETRY_TIME) ;\
until $(AVRDUDE_PROGRAMMER) -p $(AVRDUDE_MCU) -c usbasp 2>&1 | (! grep -q "could not find USB device with"); do\
printf "." ;\
sleep $(BOOTLOADER_RETRY_TIME) ;\
done ;\
printf "\n" ;\
fi
$(AVRDUDE_PROGRAMMER) -p $(AVRDUDE_MCU) -c usbasp -U flash:w:$(BUILD_DIR)/$(TARGET).hex
endef

49
platforms/avr/gpio.h Normal file
View File

@@ -0,0 +1,49 @@
/* Copyright 2021 QMK
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#pragma once
#include <avr/io.h>
#include "pin_defs.h"
typedef uint8_t pin_t;
/* Operation of GPIO by pin. */
#define setPinInput(pin) (DDRx_ADDRESS(pin) &= ~_BV((pin)&0xF), PORTx_ADDRESS(pin) &= ~_BV((pin)&0xF))
#define setPinInputHigh(pin) (DDRx_ADDRESS(pin) &= ~_BV((pin)&0xF), PORTx_ADDRESS(pin) |= _BV((pin)&0xF))
#define setPinInputLow(pin) _Static_assert(0, "AVR processors cannot implement an input as pull low")
#define setPinOutput(pin) (DDRx_ADDRESS(pin) |= _BV((pin)&0xF))
#define writePinHigh(pin) (PORTx_ADDRESS(pin) |= _BV((pin)&0xF))
#define writePinLow(pin) (PORTx_ADDRESS(pin) &= ~_BV((pin)&0xF))
#define writePin(pin, level) ((level) ? writePinHigh(pin) : writePinLow(pin))
#define readPin(pin) ((bool)(PINx_ADDRESS(pin) & _BV((pin)&0xF)))
#define togglePin(pin) (PORTx_ADDRESS(pin) ^= _BV((pin)&0xF))
/* Operation of GPIO by port. */
typedef uint8_t port_data_t;
#define readPort(port) PINx_ADDRESS(port)
#define setPortBitInput(port, bit) (DDRx_ADDRESS(port) &= ~_BV((bit)&0xF), PORTx_ADDRESS(port) &= ~_BV((bit)&0xF))
#define setPortBitInputHigh(port, bit) (DDRx_ADDRESS(port) &= ~_BV((bit)&0xF), PORTx_ADDRESS(port) |= _BV((bit)&0xF))
#define setPortBitOutput(port, bit) (DDRx_ADDRESS(port) |= _BV((bit)&0xF))
#define writePortBitLow(port, bit) (PORTx_ADDRESS(port) &= ~_BV((bit)&0xF))
#define writePortBitHigh(port, bit) (PORTx_ADDRESS(port) |= _BV((bit)&0xF))

128
platforms/avr/pin_defs.h Normal file
View File

@@ -0,0 +1,128 @@
/* Copyright 2021 QMK
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#pragma once
#include <avr/io.h>
#define PORT_SHIFTER 4 // this may be 4 for all AVR chips
// If you want to add more to this list, reference the PINx definitions in these header
// files: https://github.com/vancegroup-mirrors/avr-libc/tree/master/avr-libc/include/avr
#if defined(__AVR_ATmega32U4__) || defined(__AVR_ATmega16U4__)
# define ADDRESS_BASE 0x00
# define PINB_ADDRESS 0x3
# define PINC_ADDRESS 0x6
# define PIND_ADDRESS 0x9
# define PINE_ADDRESS 0xC
# define PINF_ADDRESS 0xF
#elif defined(__AVR_AT90USB162__) || defined(__AVR_ATmega32U2__) || defined(__AVR_ATmega16U2__) || defined(__AVR_ATmega328P__) || defined(__AVR_ATmega328__)
# define ADDRESS_BASE 0x00
# define PINB_ADDRESS 0x3
# define PINC_ADDRESS 0x6
# define PIND_ADDRESS 0x9
#elif defined(__AVR_AT90USB646__) || defined(__AVR_AT90USB647__) || defined(__AVR_AT90USB1286__) || defined(__AVR_AT90USB1287__)
# define ADDRESS_BASE 0x00
# define PINA_ADDRESS 0x0
# define PINB_ADDRESS 0x3
# define PINC_ADDRESS 0x6
# define PIND_ADDRESS 0x9
# define PINE_ADDRESS 0xC
# define PINF_ADDRESS 0xF
#elif defined(__AVR_ATmega32A__)
# define ADDRESS_BASE 0x10
# define PIND_ADDRESS 0x0
# define PINC_ADDRESS 0x3
# define PINB_ADDRESS 0x6
# define PINA_ADDRESS 0x9
#elif defined(__AVR_ATtiny85__)
# define ADDRESS_BASE 0x10
# define PINB_ADDRESS 0x6
#else
# error "Pins are not defined"
#endif
#define PINDEF(port, pin) ((PIN##port##_ADDRESS << PORT_SHIFTER) | pin)
#define _PIN_ADDRESS(p, offset) _SFR_IO8(ADDRESS_BASE + ((p) >> PORT_SHIFTER) + (offset))
// Port X Input Pins Address
#define PINx_ADDRESS(p) _PIN_ADDRESS(p, 0)
// Port X Data Direction Register, 0:input 1:output
#define DDRx_ADDRESS(p) _PIN_ADDRESS(p, 1)
// Port X Data Register
#define PORTx_ADDRESS(p) _PIN_ADDRESS(p, 2)
/* I/O pins */
#ifdef PORTA
# define A0 PINDEF(A, 0)
# define A1 PINDEF(A, 1)
# define A2 PINDEF(A, 2)
# define A3 PINDEF(A, 3)
# define A4 PINDEF(A, 4)
# define A5 PINDEF(A, 5)
# define A6 PINDEF(A, 6)
# define A7 PINDEF(A, 7)
#endif
#ifdef PORTB
# define B0 PINDEF(B, 0)
# define B1 PINDEF(B, 1)
# define B2 PINDEF(B, 2)
# define B3 PINDEF(B, 3)
# define B4 PINDEF(B, 4)
# define B5 PINDEF(B, 5)
# define B6 PINDEF(B, 6)
# define B7 PINDEF(B, 7)
#endif
#ifdef PORTC
# define C0 PINDEF(C, 0)
# define C1 PINDEF(C, 1)
# define C2 PINDEF(C, 2)
# define C3 PINDEF(C, 3)
# define C4 PINDEF(C, 4)
# define C5 PINDEF(C, 5)
# define C6 PINDEF(C, 6)
# define C7 PINDEF(C, 7)
#endif
#ifdef PORTD
# define D0 PINDEF(D, 0)
# define D1 PINDEF(D, 1)
# define D2 PINDEF(D, 2)
# define D3 PINDEF(D, 3)
# define D4 PINDEF(D, 4)
# define D5 PINDEF(D, 5)
# define D6 PINDEF(D, 6)
# define D7 PINDEF(D, 7)
#endif
#ifdef PORTE
# define E0 PINDEF(E, 0)
# define E1 PINDEF(E, 1)
# define E2 PINDEF(E, 2)
# define E3 PINDEF(E, 3)
# define E4 PINDEF(E, 4)
# define E5 PINDEF(E, 5)
# define E6 PINDEF(E, 6)
# define E7 PINDEF(E, 7)
#endif
#ifdef PORTF
# define F0 PINDEF(F, 0)
# define F1 PINDEF(F, 1)
# define F2 PINDEF(F, 2)
# define F3 PINDEF(F, 3)
# define F4 PINDEF(F, 4)
# define F5 PINDEF(F, 5)
# define F6 PINDEF(F, 6)
# define F7 PINDEF(F, 7)
#endif

21
platforms/avr/platform.c Normal file
View File

@@ -0,0 +1,21 @@
/* Copyright 2021 QMK
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#include "platform_deps.h"
void platform_setup(void) {
// do nothing
}

179
platforms/avr/platform.mk Normal file
View File

@@ -0,0 +1,179 @@
# Hey Emacs, this is a -*- makefile -*-
##############################################################################
# Compiler settings
#
CC = $(CC_PREFIX) avr-gcc
OBJCOPY = avr-objcopy
OBJDUMP = avr-objdump
SIZE = avr-size
AR = avr-ar
NM = avr-nm
HEX = $(OBJCOPY) -O $(FORMAT) -R .eeprom -R .fuse -R .lock -R .signature
EEP = $(OBJCOPY) -j .eeprom --set-section-flags=.eeprom="alloc,load" --change-section-lma .eeprom=0 --no-change-warnings -O $(FORMAT)
BIN =
COMPILEFLAGS += -funsigned-char
COMPILEFLAGS += -funsigned-bitfields
COMPILEFLAGS += -ffunction-sections
COMPILEFLAGS += -fdata-sections
COMPILEFLAGS += -fpack-struct
COMPILEFLAGS += -fshort-enums
ASFLAGS += $(AVR_ASFLAGS)
CFLAGS += $(COMPILEFLAGS) $(AVR_CFLAGS)
CFLAGS += -fno-inline-small-functions
CFLAGS += -fno-strict-aliasing
CXXFLAGS += $(COMPILEFLAGS)
CXXFLAGS += -fno-exceptions -std=c++11
LDFLAGS +=-Wl,--gc-sections
OPT_DEFS += -DF_CPU=$(F_CPU)UL
MCUFLAGS = -mmcu=$(MCU)
# List any extra directories to look for libraries here.
# Each directory must be seperated by a space.
# Use forward slashes for directory separators.
# For a directory that has spaces, enclose it in quotes.
EXTRALIBDIRS =
#---------------- External Memory Options ----------------
# 64 KB of external RAM, starting after internal RAM (ATmega128!),
# used for variables (.data/.bss) and heap (malloc()).
#EXTMEMOPTS = -Wl,-Tdata=0x801100,--defsym=__heap_end=0x80ffff
# 64 KB of external RAM, starting after internal RAM (ATmega128!),
# only used for heap (malloc()).
#EXTMEMOPTS = -Wl,--section-start,.data=0x801100,--defsym=__heap_end=0x80ffff
EXTMEMOPTS =
#---------------- Debugging Options ----------------
# Debugging format.
# Native formats for AVR-GCC's -g are dwarf-2 [default] or stabs.
# AVR Studio 4.10 requires dwarf-2.
# AVR [Extended] COFF format requires stabs, plus an avr-objcopy run.
DEBUG = dwarf-2
# For simulavr only - target MCU frequency.
DEBUG_MFREQ = $(F_CPU)
# Set the DEBUG_UI to either gdb or insight.
# DEBUG_UI = gdb
DEBUG_UI = insight
# Set the debugging back-end to either avarice, simulavr.
DEBUG_BACKEND = avarice
#DEBUG_BACKEND = simulavr
# GDB Init Filename.
GDBINIT_FILE = __avr_gdbinit
# When using avarice settings for the JTAG
JTAG_DEV = /dev/com1
# Debugging port used to communicate between GDB / avarice / simulavr.
DEBUG_PORT = 4242
# Debugging host used to communicate between GDB / avarice / simulavr, normally
# just set to localhost unless doing some sort of crazy debugging when
# avarice is running on a different computer.
DEBUG_HOST = localhost
#============================================================================
# Convert hex to bin.
bin: $(BUILD_DIR)/$(TARGET).hex
ifeq ($(BOOTLOADER),lufa-ms)
$(eval BIN_PADDING=$(shell n=`expr 32768 - $(BOOTLOADER_SIZE)` && echo $$(($$n)) || echo 0))
$(OBJCOPY) -Iihex -Obinary $(BUILD_DIR)/$(TARGET).hex $(BUILD_DIR)/$(TARGET).bin --pad-to $(BIN_PADDING)
else
$(OBJCOPY) -Iihex -Obinary $(BUILD_DIR)/$(TARGET).hex $(BUILD_DIR)/$(TARGET).bin
endif
$(COPY) $(BUILD_DIR)/$(TARGET).bin $(TARGET).bin;
# copy bin to FLASH.bin
flashbin: bin
$(COPY) $(BUILD_DIR)/$(TARGET).bin FLASH.bin;
# Generate avr-gdb config/init file which does the following:
# define the reset signal, load the target file, connect to target, and set
# a breakpoint at main().
gdb-config:
@$(REMOVE) $(GDBINIT_FILE)
@echo define reset >> $(GDBINIT_FILE)
@echo SIGNAL SIGHUP >> $(GDBINIT_FILE)
@echo end >> $(GDBINIT_FILE)
@echo file $(BUILD_DIR)/$(TARGET).elf >> $(GDBINIT_FILE)
@echo target remote $(DEBUG_HOST):$(DEBUG_PORT) >> $(GDBINIT_FILE)
ifeq ($(DEBUG_BACKEND),simulavr)
@echo load >> $(GDBINIT_FILE)
endif
@echo break main >> $(GDBINIT_FILE)
debug: gdb-config $(BUILD_DIR)/$(TARGET).elf
ifeq ($(DEBUG_BACKEND), avarice)
@echo Starting AVaRICE - Press enter when "waiting to connect" message displays.
@$(WINSHELL) /c start avarice --jtag $(JTAG_DEV) --erase --program --file \
$(BUILD_DIR)/$(TARGET).elf $(DEBUG_HOST):$(DEBUG_PORT)
@$(WINSHELL) /c pause
else
@$(WINSHELL) /c start simulavr --gdbserver --device $(MCU) --clock-freq \
$(DEBUG_MFREQ) --port $(DEBUG_PORT)
endif
@$(WINSHELL) /c start avr-$(DEBUG_UI) --command=$(GDBINIT_FILE)
# Convert ELF to COFF for use in debugging / simulating in AVR Studio or VMLAB.
COFFCONVERT = $(OBJCOPY) --debugging
COFFCONVERT += --change-section-address .data-0x800000
COFFCONVERT += --change-section-address .bss-0x800000
COFFCONVERT += --change-section-address .noinit-0x800000
COFFCONVERT += --change-section-address .eeprom-0x810000
coff: $(BUILD_DIR)/$(TARGET).elf
@$(SECHO) $(MSG_COFF) $(BUILD_DIR)/$(TARGET).cof
$(COFFCONVERT) -O coff-avr $< $(BUILD_DIR)/$(TARGET).cof
extcoff: $(BUILD_DIR)/$(TARGET).elf
@$(SECHO) $(MSG_EXTENDED_COFF) $(BUILD_DIR)/$(TARGET).cof
$(COFFCONVERT) -O coff-ext-avr $< $(BUILD_DIR)/$(TARGET).cof
ifeq ($(strip $(BOOTLOADER)), qmk-dfu)
QMK_BOOTLOADER_TYPE = DFU
else ifeq ($(strip $(BOOTLOADER)), qmk-hid)
QMK_BOOTLOADER_TYPE = HID
endif
bootloader:
ifeq ($(strip $(QMK_BOOTLOADER_TYPE)),)
$(error Please set BOOTLOADER to "qmk-dfu" or "qmk-hid" first!)
else
make -C lib/lufa/Bootloaders/$(QMK_BOOTLOADER_TYPE)/ clean
$(QMK_BIN) generate-dfu-header --quiet --keyboard $(KEYBOARD) --output lib/lufa/Bootloaders/$(QMK_BOOTLOADER_TYPE)/Keyboard.h
$(eval MAX_SIZE=$(shell n=`$(CC) -E -mmcu=$(MCU) -D__ASSEMBLER__ $(CFLAGS) $(OPT_DEFS) platforms/avr/bootloader_size.c 2> /dev/null | sed -ne 's/\r//;/^#/n;/^AVR_SIZE:/,$${s/^AVR_SIZE: //;p;}'` && echo $$(($$n)) || echo 0))
$(eval PROGRAM_SIZE_KB=$(shell n=`expr $(MAX_SIZE) / 1024` && echo $$(($$n)) || echo 0))
$(eval BOOT_SECTION_SIZE_KB=$(shell n=`expr $(BOOTLOADER_SIZE) / 1024` && echo $$(($$n)) || echo 0))
$(eval FLASH_SIZE_KB=$(shell n=`expr $(PROGRAM_SIZE_KB) + $(BOOT_SECTION_SIZE_KB)` && echo $$(($$n)) || echo 0))
make -C lib/lufa/Bootloaders/$(QMK_BOOTLOADER_TYPE)/ MCU=$(MCU) ARCH=$(ARCH) F_CPU=$(F_CPU) FLASH_SIZE_KB=$(FLASH_SIZE_KB) BOOT_SECTION_SIZE_KB=$(BOOT_SECTION_SIZE_KB)
printf "Bootloader$(QMK_BOOTLOADER_TYPE).hex copied to $(TARGET)_bootloader.hex\n"
cp lib/lufa/Bootloaders/$(QMK_BOOTLOADER_TYPE)/Bootloader$(QMK_BOOTLOADER_TYPE).hex $(TARGET)_bootloader.hex
endif
production: $(BUILD_DIR)/$(TARGET).hex bootloader cpfirmware
@cat $(BUILD_DIR)/$(TARGET).hex | awk '/^:00000001FF/ == 0' > $(TARGET)_production.hex
@cat $(TARGET)_bootloader.hex >> $(TARGET)_production.hex
echo "File sizes:"
$(SIZE) $(TARGET).hex $(TARGET)_bootloader.hex $(TARGET)_production.hex

20
platforms/avr/platform_deps.h Normal file
View File

@@ -0,0 +1,20 @@
/* Copyright 2021 QMK
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#pragma once
#include <avr/pgmspace.h>
#include <avr/io.h>
#include <avr/interrupt.h>

20
platforms/avr/printf.c Normal file
View File

@@ -0,0 +1,20 @@
/*
Copyright 2011 Jun Wako <wakojun@gmail.com>
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#include "xprintf.h"
#include "sendchar.h"
void print_set_sendchar(sendchar_func_t func) { xdev_out(func); }

2
platforms/avr/printf.mk Normal file
View File

@@ -0,0 +1,2 @@
TMK_COMMON_SRC += $(PLATFORM_COMMON_DIR)/xprintf.S
TMK_COMMON_SRC += $(PLATFORM_COMMON_DIR)/printf.c

124
platforms/avr/sleep_led.c Normal file
View File

@@ -0,0 +1,124 @@
#include <stdint.h>
#include <avr/io.h>
#include <avr/interrupt.h>
#include <avr/pgmspace.h>
#include "led.h"
#include "sleep_led.h"
#ifndef SLEEP_LED_TIMER
# define SLEEP_LED_TIMER 1
#endif
#if SLEEP_LED_TIMER == 1
# define TCCRxB TCCR1B
# define TIMERx_COMPA_vect TIMER1_COMPA_vect
# if defined(__AVR_ATmega32A__) // This MCU has only one TIMSK register
# define TIMSKx TIMSK
# else
# define TIMSKx TIMSK1
# endif
# define OCIExA OCIE1A
# define OCRxx OCR1A
#elif SLEEP_LED_TIMER == 3
# define TCCRxB TCCR3B
# define TIMERx_COMPA_vect TIMER3_COMPA_vect
# define TIMSKx TIMSK3
# define OCIExA OCIE3A
# define OCRxx OCR3A
#else
error("Invalid SLEEP_LED_TIMER config")
#endif
/* Software PWM
* ______ ______ __
* | ON |___OFF___| ON |___OFF___| ....
* |<-------------->|<-------------->|<- ....
* PWM period PWM period
*
* 256 interrupts/period[resolution]
* 64 periods/second[frequency]
* 256*64 interrupts/second
* F_CPU/(256*64) clocks/interrupt
*/
#define SLEEP_LED_TIMER_TOP F_CPU / (256 * 64)
/** \brief Sleep LED initialization
*
* FIXME: needs doc
*/
void sleep_led_init(void) {
/* Timer1 setup */
/* CTC mode */
TCCRxB |= _BV(WGM12);
/* Clock selelct: clk/1 */
TCCRxB |= _BV(CS10);
/* Set TOP value */
uint8_t sreg = SREG;
cli();
OCRxx = SLEEP_LED_TIMER_TOP;
SREG = sreg;
}
/** \brief Sleep LED enable
*
* FIXME: needs doc
*/
void sleep_led_enable(void) {
/* Enable Compare Match Interrupt */
TIMSKx |= _BV(OCIExA);
}
/** \brief Sleep LED disable
*
* FIXME: needs doc
*/
void sleep_led_disable(void) {
/* Disable Compare Match Interrupt */
TIMSKx &= ~_BV(OCIExA);
}
/** \brief Sleep LED toggle
*
* FIXME: needs doc
*/
void sleep_led_toggle(void) {
/* Disable Compare Match Interrupt */
TIMSKx ^= _BV(OCIExA);
}
/** \brief Breathing Sleep LED brighness(PWM On period) table
*
* (64[steps] * 4[duration]) / 64[PWM periods/s] = 4 second breath cycle
*
* https://www.wolframalpha.com/input/?i=sin%28x%2F64*pi%29**8+*+255%2C+x%3D0+to+63
* (0..63).each {|x| p ((sin(x/64.0*PI)**8)*255).to_i }
*/
static const uint8_t breathing_table[64] PROGMEM = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 4, 6, 10, 15, 23, 32, 44, 58, 74, 93, 113, 135, 157, 179, 199, 218, 233, 245, 252, 255, 252, 245, 233, 218, 199, 179, 157, 135, 113, 93, 74, 58, 44, 32, 23, 15, 10, 6, 4, 2, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
ISR(TIMERx_COMPA_vect) {
/* Software PWM
* timer:1111 1111 1111 1111
* \_____/\/ \_______/____ count(0-255)
* \ \______________ duration of step(4)
* \__________________ index of step table(0-63)
*/
static union {
uint16_t row;
struct {
uint8_t count : 8;
uint8_t duration : 2;
uint8_t index : 6;
} pwm;
} timer = {.row = 0};
timer.row++;
// LED on
if (timer.pwm.count == 0) {
led_set(1 << USB_LED_CAPS_LOCK);
}
// LED off
if (timer.pwm.count == pgm_read_byte(&breathing_table[timer.pwm.index])) {
led_set(0);
}
}

152
platforms/avr/suspend.c Normal file
View File

@@ -0,0 +1,152 @@
#include <stdbool.h>
#include <avr/sleep.h>
#include <avr/wdt.h>
#include <avr/interrupt.h>
#include "matrix.h"
#include "action.h"
#include "suspend.h"
#include "timer.h"
#include "led.h"
#include "host.h"
#ifdef PROTOCOL_LUFA
# include "lufa.h"
#endif
#ifdef PROTOCOL_VUSB
# include "vusb.h"
#endif
/** \brief Suspend idle
*
* FIXME: needs doc
*/
void suspend_idle(uint8_t time) {
cli();
set_sleep_mode(SLEEP_MODE_IDLE);
sleep_enable();
sei();
sleep_cpu();
sleep_disable();
}
// TODO: This needs some cleanup
#if !defined(NO_SUSPEND_POWER_DOWN) && defined(WDT_vect)
// clang-format off
#define wdt_intr_enable(value) \
__asm__ __volatile__ ( \
"in __tmp_reg__,__SREG__" "\n\t" \
"cli" "\n\t" \
"wdr" "\n\t" \
"sts %0,%1" "\n\t" \
"out __SREG__,__tmp_reg__" "\n\t" \
"sts %0,%2" "\n\t" \
: /* no outputs */ \
: "M" (_SFR_MEM_ADDR(_WD_CONTROL_REG)), \
"r" (_BV(_WD_CHANGE_BIT) | _BV(WDE)), \
"r" ((uint8_t) ((value & 0x08 ? _WD_PS3_MASK : 0x00) | _BV(WDIE) | (value & 0x07))) \
: "r0" \
)
// clang-format on
/** \brief Power down MCU with watchdog timer
*
* wdto: watchdog timer timeout defined in <avr/wdt.h>
* WDTO_15MS
* WDTO_30MS
* WDTO_60MS
* WDTO_120MS
* WDTO_250MS
* WDTO_500MS
* WDTO_1S
* WDTO_2S
* WDTO_4S
* WDTO_8S
*/
static uint8_t wdt_timeout = 0;
/** \brief Power down
*
* FIXME: needs doc
*/
static void power_down(uint8_t wdto) {
wdt_timeout = wdto;
// Watchdog Interrupt Mode
wdt_intr_enable(wdto);
// TODO: more power saving
// See PicoPower application note
// - I/O port input with pullup
// - prescale clock
// - BOD disable
// - Power Reduction Register PRR
set_sleep_mode(SLEEP_MODE_PWR_DOWN);
sleep_enable();
sei();
sleep_cpu();
sleep_disable();
// Disable watchdog after sleep
wdt_disable();
}
#endif
/** \brief Suspend power down
*
* FIXME: needs doc
*/
void suspend_power_down(void) {
#ifdef PROTOCOL_LUFA
if (USB_DeviceState == DEVICE_STATE_Configured) return;
#endif
#ifdef PROTOCOL_VUSB
if (!vusb_suspended) return;
#endif
suspend_power_down_quantum();
#ifndef NO_SUSPEND_POWER_DOWN
// Enter sleep state if possible (ie, the MCU has a watchdog timeout interrupt)
# if defined(WDT_vect)
power_down(WDTO_15MS);
# endif
#endif
}
__attribute__((weak)) void matrix_power_up(void) {}
__attribute__((weak)) void matrix_power_down(void) {}
bool suspend_wakeup_condition(void) {
matrix_power_up();
matrix_scan();
matrix_power_down();
for (uint8_t r = 0; r < MATRIX_ROWS; r++) {
if (matrix_get_row(r)) return true;
}
return false;
}
/** \brief run immediately after wakeup
*
* FIXME: needs doc
*/
void suspend_wakeup_init(void) {
// clear keyboard state
clear_keyboard();
suspend_wakeup_init_quantum();
}
#if !defined(NO_SUSPEND_POWER_DOWN) && defined(WDT_vect)
/* watchdog timeout */
ISR(WDT_vect) {
// compensate timer for sleep
switch (wdt_timeout) {
case WDTO_15MS:
timer_count += 15 + 2; // WDTO_15MS + 2(from observation)
break;
default:;
}
}
#endif

133
platforms/avr/timer.c Normal file
View File

@@ -0,0 +1,133 @@
/*
Copyright 2011 Jun Wako <wakojun@gmail.com>
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#include <avr/io.h>
#include <avr/interrupt.h>
#include <util/atomic.h>
#include <stdint.h>
#include "timer_avr.h"
#include "timer.h"
// counter resolution 1ms
// NOTE: union { uint32_t timer32; struct { uint16_t dummy; uint16_t timer16; }}
volatile uint32_t timer_count;
/** \brief timer initialization
*
* FIXME: needs doc
*/
void timer_init(void) {
#if TIMER_PRESCALER == 1
uint8_t prescaler = _BV(CS00);
#elif TIMER_PRESCALER == 8
uint8_t prescaler = _BV(CS01);
#elif TIMER_PRESCALER == 64
uint8_t prescaler = _BV(CS00) | _BV(CS01);
#elif TIMER_PRESCALER == 256
uint8_t prescaler = _BV(CS02);
#elif TIMER_PRESCALER == 1024
uint8_t prescaler = _BV(CS00) | _BV(CS02);
#else
# error "Timer prescaler value is not valid"
#endif
#if defined(__AVR_ATmega32A__)
// Timer0 CTC mode
TCCR0 = _BV(WGM01) | prescaler;
OCR0 = TIMER_RAW_TOP;
TIMSK = _BV(OCIE0);
#elif defined(__AVR_ATtiny85__)
// Timer0 CTC mode
TCCR0A = _BV(WGM01);
TCCR0B = prescaler;
OCR0A = TIMER_RAW_TOP;
TIMSK = _BV(OCIE0A);
#else
// Timer0 CTC mode
TCCR0A = _BV(WGM01);
TCCR0B = prescaler;
OCR0A = TIMER_RAW_TOP;
TIMSK0 = _BV(OCIE0A);
#endif
}
/** \brief timer clear
*
* FIXME: needs doc
*/
inline void timer_clear(void) {
ATOMIC_BLOCK(ATOMIC_RESTORESTATE) { timer_count = 0; }
}
/** \brief timer read
*
* FIXME: needs doc
*/
inline uint16_t timer_read(void) {
uint32_t t;
ATOMIC_BLOCK(ATOMIC_RESTORESTATE) { t = timer_count; }
return (t & 0xFFFF);
}
/** \brief timer read32
*
* FIXME: needs doc
*/
inline uint32_t timer_read32(void) {
uint32_t t;
ATOMIC_BLOCK(ATOMIC_RESTORESTATE) { t = timer_count; }
return t;
}
/** \brief timer elapsed
*
* FIXME: needs doc
*/
inline uint16_t timer_elapsed(uint16_t last) {
uint32_t t;
ATOMIC_BLOCK(ATOMIC_RESTORESTATE) { t = timer_count; }
return TIMER_DIFF_16((t & 0xFFFF), last);
}
/** \brief timer elapsed32
*
* FIXME: needs doc
*/
inline uint32_t timer_elapsed32(uint32_t last) {
uint32_t t;
ATOMIC_BLOCK(ATOMIC_RESTORESTATE) { t = timer_count; }
return TIMER_DIFF_32(t, last);
}
// excecuted once per 1ms.(excess for just timer count?)
#ifndef __AVR_ATmega32A__
# define TIMER_INTERRUPT_VECTOR TIMER0_COMPA_vect
#else
# define TIMER_INTERRUPT_VECTOR TIMER0_COMP_vect
#endif
ISR(TIMER_INTERRUPT_VECTOR, ISR_NOBLOCK) { timer_count++; }

39
platforms/avr/timer_avr.h Normal file
View File

@@ -0,0 +1,39 @@
/*
Copyright 2011 Jun Wako <wakojun@gmail.com>
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#pragma once
#include <stdint.h>
#ifndef TIMER_PRESCALER
# if F_CPU > 16000000
# define TIMER_PRESCALER 256
# elif F_CPU > 2000000
# define TIMER_PRESCALER 64
# elif F_CPU > 250000
# define TIMER_PRESCALER 8
# else
# define TIMER_PRESCALER 1
# endif
#endif
#define TIMER_RAW_FREQ (F_CPU / TIMER_PRESCALER)
#define TIMER_RAW TCNT0
#define TIMER_RAW_TOP (TIMER_RAW_FREQ / 1000)
#if (TIMER_RAW_TOP > 255)
# error "Timer0 can't count 1ms at this clock freq. Use larger prescaler."
#endif

498
platforms/avr/xprintf.S Normal file
View File

@@ -0,0 +1,498 @@
;---------------------------------------------------------------------------;
; Extended itoa, puts, printf and atoi (C)ChaN, 2011
;---------------------------------------------------------------------------;
// Base size is 152 bytes
#define CR_CRLF 0 // Convert \n to \r\n (+10 bytes)
#define USE_XPRINTF 1 // Enable xprintf function (+194 bytes)
#define USE_XSPRINTF 0 // Add xsprintf function (+78 bytes)
#define USE_XFPRINTF 0 // Add xfprintf function (+54 bytes)
#define USE_XATOI 0 // Enable xatoi function (+182 bytes)
#if FLASHEND > 0x1FFFF
#error xitoa module does not support 256K devices
#endif
.nolist
#include <avr/io.h> // Include device specific definitions.
.list
#ifdef SPM_PAGESIZE // Recent devices have "lpm Rd,Z+" and "movw".
.macro _LPMI reg
lpm \reg, Z+
.endm
.macro _MOVW dh,dl, sh,sl
movw \dl, \sl
.endm
#else // Earlier devices do not have "lpm Rd,Z+" nor "movw".
.macro _LPMI reg
lpm
mov \reg, r0
adiw ZL, 1
.endm
.macro _MOVW dh,dl, sh,sl
mov \dl, \sl
mov \dh, \sh
.endm
#endif
;---------------------------------------------------------------------------
; Stub function to forward to user output function
;
;Prototype: void xputc (char chr // a character to be output
; );
;Size: 12/12 words
.section .bss
.global xfunc_out ; xfunc_out must be initialized before using this module.
xfunc_out: .ds.w 1
.section .text
.func xputc
.global xputc
xputc:
#if CR_CRLF
cpi r24, 10 ;LF --> CRLF
brne 1f ;
ldi r24, 13 ;
rcall 1f ;
ldi r24, 10 ;/
1:
#endif
push ZH
push ZL
lds ZL, xfunc_out+0 ;Pointer to the registered output function.
lds ZH, xfunc_out+1 ;/
sbiw ZL, 0 ;Skip if null
breq 2f ;/
icall
2: pop ZL
pop ZH
ret
.endfunc
;---------------------------------------------------------------------------
; Direct ROM string output
;
;Prototype: void xputs (const char *str_p // rom string to be output
; );
.func xputs
.global xputs
xputs:
_MOVW ZH,ZL, r25,r24 ; Z = pointer to rom string
1: _LPMI r24
cpi r24, 0
breq 2f
rcall xputc
rjmp 1b
2: ret
.endfunc
;---------------------------------------------------------------------------
; Extended direct numeral string output (32bit version)
;
;Prototype: void xitoa (long value, // value to be output
; char radix, // radix
; char width); // minimum width
;
.func xitoa
.global xitoa
xitoa:
;r25:r22 = value, r20 = base, r18 = digits
clr r31 ;r31 = stack level
ldi r30, ' ' ;r30 = sign
ldi r19, ' ' ;r19 = filler
sbrs r20, 7 ;When base indicates signd format and the value
rjmp 0f ;is minus, add a '-'.
neg r20 ;
sbrs r25, 7 ;
rjmp 0f ;
ldi r30, '-' ;
com r22 ;
com r23 ;
com r24 ;
com r25 ;
adc r22, r1 ;
adc r23, r1 ;
adc r24, r1 ;
adc r25, r1 ;/
0: sbrs r18, 7 ;When digits indicates zero filled,
rjmp 1f ;filler is '0'.
neg r18 ;
ldi r19, '0' ;/
;----- string conversion loop
1: ldi r21, 32 ;r26 = r25:r22 % r20
clr r26 ;r25:r22 /= r20
2: lsl r22 ;
rol r23 ;
rol r24 ;
rol r25 ;
rol r26 ;
cp r26, r20 ;
brcs 3f ;
sub r26, r20 ;
inc r22 ;
3: dec r21 ;
brne 2b ;/
cpi r26, 10 ;r26 is a numeral digit '0'-'F'
brcs 4f ;
subi r26, -7 ;
4: subi r26, -'0' ;/
push r26 ;Stack it
inc r31 ;/
cp r22, r1 ;Repeat until r25:r22 gets zero
cpc r23, r1 ;
cpc r24, r1 ;
cpc r25, r1 ;
brne 1b ;/
cpi r30, '-' ;Minus sign if needed
brne 5f ;
push r30 ;
inc r31 ;/
5: cp r31, r18 ;Filler
brcc 6f ;
push r19 ;
inc r31 ;
rjmp 5b ;/
6: pop r24 ;Flush stacked digits and exit
rcall xputc ;
dec r31 ;
brne 6b ;/
ret
.endfunc
;---------------------------------------------------------------------------;
; Formatted string output (16/32bit version)
;
;Prototype:
; void __xprintf (const char *format_p, ...);
; void __xsprintf(char*, const char *format_p, ...);
; void __xfprintf(void(*func)(char), const char *format_p, ...);
;
#if USE_XPRINTF
.func xvprintf
xvprintf:
ld ZL, Y+ ;Z = pointer to format string
ld ZH, Y+ ;/
0: _LPMI r24 ;Get a format char
cpi r24, 0 ;End of format string?
breq 90f ;/
cpi r24, '%' ;Is format?
breq 20f ;/
1: rcall xputc ;Put a normal character
rjmp 0b ;/
90: ret
20: ldi r18, 0 ;r18: digits
clt ;T: filler
_LPMI r21 ;Get flags
cpi r21, '%' ;Is a %?
breq 1b ;/
cpi r21, '0' ;Zero filled?
brne 23f ;
set ;/
22: _LPMI r21 ;Get width
23: cpi r21, '9'+1 ;
brcc 24f ;
subi r21, '0' ;
brcs 90b ;
lsl r18 ;
mov r0, r18 ;
lsl r18 ;
lsl r18 ;
add r18, r0 ;
add r18, r21 ;
rjmp 22b ;/
24: brtc 25f ;get value (low word)
neg r18 ;
25: ld r24, Y+ ;
ld r25, Y+ ;/
cpi r21, 'c' ;Is type character?
breq 1b ;/
cpi r21, 's' ;Is type RAM string?
breq 50f ;/
cpi r21, 'S' ;Is type ROM string?
breq 60f ;/
_MOVW r23,r22,r25,r24 ;r25:r22 = value
clr r24 ;
clr r25 ;
clt ;/
cpi r21, 'l' ;Is long int?
brne 26f ;
ld r24, Y+ ;get value (high word)
ld r25, Y+ ;
set ;
_LPMI r21 ;/
26: cpi r21, 'd' ;Is type signed decimal?
brne 27f ;/
ldi r20, -10 ;
brts 40f ;
sbrs r23, 7 ;
rjmp 40f ;
ldi r24, -1 ;
ldi r25, -1 ;
rjmp 40f ;/
27: cpi r21, 'u' ;Is type unsigned decimal?
ldi r20, 10 ;
breq 40f ;/
cpi r21, 'X' ;Is type hexdecimal?
ldi r20, 16 ;
breq 40f ;/
cpi r21, 'b' ;Is type binary?
ldi r20, 2 ;
breq 40f ;/
ret ;abort
40: push ZH ;Output the value
push ZL ;
rcall xitoa ;
42: pop ZL ;
pop ZH ;
rjmp 0b ;/
50: push ZH ;Put a string on the RAM
push ZL
_MOVW ZH,ZL, r25,r24
51: ld r24, Z+
cpi r24, 0
breq 42b
rcall xputc
rjmp 51b
60: push ZH ;Put a string on the ROM
push ZL
rcall xputs
rjmp 42b
.endfunc
.func __xprintf
.global __xprintf
__xprintf:
push YH
push YL
in YL, _SFR_IO_ADDR(SPL)
#ifdef SPH
in YH, _SFR_IO_ADDR(SPH)
#else
clr YH
#endif
adiw YL, 5 ;Y = pointer to arguments
rcall xvprintf
pop YL
pop YH
ret
.endfunc
#if USE_XSPRINTF
.func __xsprintf
putram:
_MOVW ZH,ZL, r15,r14
st Z+, r24
_MOVW r15,r14, ZH,ZL
ret
.global __xsprintf
__xsprintf:
push YH
push YL
in YL, _SFR_IO_ADDR(SPL)
#ifdef SPH
in YH, _SFR_IO_ADDR(SPH)
#else
clr YH
#endif
adiw YL, 5 ;Y = pointer to arguments
lds ZL, xfunc_out+0 ;Save registered output function
lds ZH, xfunc_out+1 ;
push ZL ;
push ZH ;/
ldi ZL, lo8(pm(putram));Set local output function
ldi ZH, hi8(pm(putram));
sts xfunc_out+0, ZL ;
sts xfunc_out+1, ZH ;/
push r15 ;Initialize pointer to string buffer
push r14 ;
ld r14, Y+ ;
ld r15, Y+ ;/
rcall xvprintf
_MOVW ZH,ZL, r15,r14 ;Terminate string
st Z, r1 ;
pop r14 ;
pop r15 ;/
pop ZH ;Restore registered output function
pop ZL ;
sts xfunc_out+0, ZL ;
sts xfunc_out+1, ZH ;/
pop YL
pop YH
ret
.endfunc
#endif
#if USE_XFPRINTF
.func __xfprintf
.global __xfprintf
__xfprintf:
push YH
push YL
in YL, _SFR_IO_ADDR(SPL)
#ifdef SPH
in YH, _SFR_IO_ADDR(SPH)
#else
clr YH
#endif
adiw YL, 5 ;Y = pointer to arguments
lds ZL, xfunc_out+0 ;Save registered output function
lds ZH, xfunc_out+1 ;
push ZL ;
push ZH ;/
ld ZL, Y+ ;Set output function
ld ZH, Y+ ;
sts xfunc_out+0, ZL ;
sts xfunc_out+1, ZH ;/
rcall xvprintf
pop ZH ;Restore registered output function
pop ZL ;
sts xfunc_out+0, ZL ;
sts xfunc_out+1, ZH ;/
pop YL
pop YH
ret
.endfunc
#endif
#endif
;---------------------------------------------------------------------------
; Extended numeral string input
;
;Prototype:
; char xatoi ( /* 1: Successful, 0: Failed */
; const char **str, /* pointer to pointer to source string */
; long *res /* result */
; );
;
#if USE_XATOI
.func xatoi
.global xatoi
xatoi:
_MOVW r1, r0, r23, r22
_MOVW XH, XL, r25, r24
ld ZL, X+
ld ZH, X+
clr r18 ;r21:r18 = 0;
clr r19 ;
clr r20 ;
clr r21 ;/
clt ;T = 0;
ldi r25, 10 ;r25 = 10;
rjmp 41f ;/
40: adiw ZL, 1 ;Z++;
41: ld r22, Z ;r22 = *Z;
cpi r22, ' ' ;if(r22 == ' ') continue
breq 40b ;/
brcs 70f ;if(r22 < ' ') error;
cpi r22, '-' ;if(r22 == '-') {
brne 42f ; T = 1;
set ; continue;
rjmp 40b ;}
42: cpi r22, '9'+1 ;if(r22 > '9') error;
brcc 70f ;/
cpi r22, '0' ;if(r22 < '0') error;
brcs 70f ;/
brne 51f ;if(r22 > '0') cv_start;
ldi r25, 8 ;r25 = 8;
adiw ZL, 1 ;r22 = *(++Z);
ld r22, Z ;/
cpi r22, ' '+1 ;if(r22 <= ' ') exit;
brcs 80f ;/
cpi r22, 'b' ;if(r22 == 'b') {
brne 43f ; r25 = 2;
ldi r25, 2 ; cv_start;
rjmp 50f ;}
43: cpi r22, 'x' ;if(r22 != 'x') error;
brne 51f ;/
ldi r25, 16 ;r25 = 16;
50: adiw ZL, 1 ;Z++;
ld r22, Z ;r22 = *Z;
51: cpi r22, ' '+1 ;if(r22 <= ' ') break;
brcs 80f ;/
cpi r22, 'a' ;if(r22 >= 'a') r22 =- 0x20;
brcs 52f ;
subi r22, 0x20 ;/
52: subi r22, '0' ;if((r22 -= '0') < 0) error;
brcs 70f ;/
cpi r22, 10 ;if(r22 >= 10) {
brcs 53f ; r22 -= 7;
subi r22, 7 ; if(r22 < 10)
cpi r22, 10 ;
brcs 70f ;}
53: cp r22, r25 ;if(r22 >= r25) error;
brcc 70f ;/
60: ldi r24, 33 ;r21:r18 *= r25;
sub r23, r23 ;
61: brcc 62f ;
add r23, r25 ;
62: lsr r23 ;
ror r21 ;
ror r20 ;
ror r19 ;
ror r18 ;
dec r24 ;
brne 61b ;/
add r18, r22 ;r21:r18 += r22;
adc r19, r24 ;
adc r20, r24 ;
adc r21, r24 ;/
rjmp 50b ;repeat
70: ldi r24, 0
rjmp 81f
80: ldi r24, 1
81: brtc 82f
clr r22
com r18
com r19
com r20
com r21
adc r18, r22
adc r19, r22
adc r20, r22
adc r21, r22
82: st -X, ZH
st -X, ZL
_MOVW XH, XL, r1, r0
st X+, r18
st X+, r19
st X+, r20
st X+, r21
clr r1
ret
.endfunc
#endif

103
platforms/avr/xprintf.h Normal file
View File

@@ -0,0 +1,103 @@
/*---------------------------------------------------------------------------
Extended itoa, puts and printf (C)ChaN, 2011
-----------------------------------------------------------------------------*/
#pragma once
#include <inttypes.h>
#include <avr/pgmspace.h>
#ifdef __cplusplus
extern "C" {
#endif
extern void (*xfunc_out)(uint8_t);
#define xdev_out(func) xfunc_out = (void (*)(uint8_t))(func)
/* This is a pointer to user defined output function. It must be initialized
before using this modle.
*/
void xputc(char chr);
/* This is a stub function to forward outputs to user defined output function.
All outputs from this module are output via this function.
*/
/*-----------------------------------------------------------------------------*/
void xputs(const char *string_p);
/* The string placed in the ROM is forwarded to xputc() directly.
*/
/*-----------------------------------------------------------------------------*/
void xitoa(long value, char radix, char width);
/* Extended itoa().
value radix width output
100 10 6 " 100"
100 10 -6 "000100"
100 10 0 "100"
4294967295 10 0 "4294967295"
4294967295 -10 0 "-1"
655360 16 -8 "000A0000"
1024 16 0 "400"
0x55 2 -8 "01010101"
*/
/*-----------------------------------------------------------------------------*/
#define xprintf(format, ...) __xprintf(PSTR(format), ##__VA_ARGS__)
#define xsprintf(str, format, ...) __xsprintf(str, PSTR(format), ##__VA_ARGS__)
#define xfprintf(func, format, ...) __xfprintf(func, PSTR(format), ##__VA_ARGS__)
void __xprintf(const char *format_p, ...); /* Send formatted string to the registered device */
// void __xsprintf(char*, const char *format_p, ...); /* Put formatted string to the memory */
// void __xfprintf(void(*func)(uint8_t), const char *format_p, ...); /* Send formatted string to the specified device */
/* Format string is placed in the ROM. The format flags is similar to printf().
%[flag][width][size]type
flag
A '0' means filled with '0' when output is shorter than width.
' ' is used in default. This is effective only numeral type.
width
Minimum width in decimal number. This is effective only numeral type.
Default width is zero.
size
A 'l' means the argument is long(32bit). Default is short(16bit).
This is effective only numeral type.
type
'c' : Character, argument is the value
's' : String placed on the RAM, argument is the pointer
'S' : String placed on the ROM, argument is the pointer
'd' : Signed decimal, argument is the value
'u' : Unsigned decimal, argument is the value
'X' : Hexdecimal, argument is the value
'b' : Binary, argument is the value
'%' : '%'
*/
/*-----------------------------------------------------------------------------*/
char xatoi(char **str, long *ret);
/* Get value of the numeral string.
str
Pointer to pointer to source string
"0b11001010" binary
"0377" octal
"0xff800" hexdecimal
"1250000" decimal
"-25000" decimal
ret
Pointer to return value
*/
#ifdef __cplusplus
}
#endif

21
platforms/bootloader.h Normal file
View File

@@ -0,0 +1,21 @@
/*
Copyright 2011 Jun Wako <wakojun@gmail.com>
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#pragma once
/* give code for your bootloader to come up if needed */
void bootloader_jump(void);

19
platforms/chibios/_timer.h Normal file
View File

@@ -0,0 +1,19 @@
/* Copyright 2021 Simon Arlott
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#pragma once
// The platform is 32-bit, so prefer 32-bit timers to avoid overflow
#define FAST_TIMER_T_SIZE 32

89
platforms/chibios/_wait.c Normal file
View File

@@ -0,0 +1,89 @@
/* Copyright 2021 QMK
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef __OPTIMIZE__
# pragma message "Compiler optimizations disabled; wait_cpuclock() won't work as designed"
#endif
#define CLOCK_DELAY_NOP8 "nop\n\t nop\n\t nop\n\t nop\n\t nop\n\t nop\n\t nop\n\t nop\n\t"
__attribute__((always_inline)) static inline void wait_cpuclock(unsigned int n) { /* n: 1..135 */
/* The argument n must be a constant expression.
* That way, compiler optimization will remove unnecessary code. */
if (n < 1) {
return;
}
if (n > 8) {
unsigned int n8 = n / 8;
n = n - n8 * 8;
switch (n8) {
case 16:
asm volatile(CLOCK_DELAY_NOP8::: "memory");
case 15:
asm volatile(CLOCK_DELAY_NOP8::: "memory");
case 14:
asm volatile(CLOCK_DELAY_NOP8::: "memory");
case 13:
asm volatile(CLOCK_DELAY_NOP8::: "memory");
case 12:
asm volatile(CLOCK_DELAY_NOP8::: "memory");
case 11:
asm volatile(CLOCK_DELAY_NOP8::: "memory");
case 10:
asm volatile(CLOCK_DELAY_NOP8::: "memory");
case 9:
asm volatile(CLOCK_DELAY_NOP8::: "memory");
case 8:
asm volatile(CLOCK_DELAY_NOP8::: "memory");
case 7:
asm volatile(CLOCK_DELAY_NOP8::: "memory");
case 6:
asm volatile(CLOCK_DELAY_NOP8::: "memory");
case 5:
asm volatile(CLOCK_DELAY_NOP8::: "memory");
case 4:
asm volatile(CLOCK_DELAY_NOP8::: "memory");
case 3:
asm volatile(CLOCK_DELAY_NOP8::: "memory");
case 2:
asm volatile(CLOCK_DELAY_NOP8::: "memory");
case 1:
asm volatile(CLOCK_DELAY_NOP8::: "memory");
case 0:
break;
}
}
switch (n) {
case 8:
asm volatile("nop" ::: "memory");
case 7:
asm volatile("nop" ::: "memory");
case 6:
asm volatile("nop" ::: "memory");
case 5:
asm volatile("nop" ::: "memory");
case 4:
asm volatile("nop" ::: "memory");
case 3:
asm volatile("nop" ::: "memory");
case 2:
asm volatile("nop" ::: "memory");
case 1:
asm volatile("nop" ::: "memory");
case 0:
break;
}
}

60
platforms/chibios/_wait.h Normal file
View File

@@ -0,0 +1,60 @@
/* Copyright 2021 QMK
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#pragma once
#include <ch.h>
#include <hal.h>
/* chThdSleepX of zero maps to infinite - so we map to a tiny delay to still yield */
#define wait_ms(ms) \
do { \
if (ms != 0) { \
chThdSleepMilliseconds(ms); \
} else { \
chThdSleepMicroseconds(1); \
} \
} while (0)
#ifdef WAIT_US_TIMER
void wait_us(uint16_t duration);
#else
# define wait_us(us) \
do { \
if (us != 0) { \
chThdSleepMicroseconds(us); \
} else { \
chThdSleepMicroseconds(1); \
} \
} while (0)
#endif
#include "_wait.c"
/* For GPIOs on ARM-based MCUs, the input pins are sampled by the clock of the bus
* to which the GPIO is connected.
* The connected buses differ depending on the various series of MCUs.
* And since the instruction execution clock of the CPU and the bus clock of GPIO are different,
* there is a delay of several clocks to read the change of the input signal.
*
* Define this delay with the GPIO_INPUT_PIN_DELAY macro.
* If the GPIO_INPUT_PIN_DELAY macro is not defined, the following default values will be used.
* (A fairly large value of 0.25 microseconds is set.)
*/
#ifndef GPIO_INPUT_PIN_DELAY
# define GPIO_INPUT_PIN_DELAY (CPU_CLOCK / 1000000L / 4)
#endif
#define waitInputPinDelay() wait_cpuclock(GPIO_INPUT_PIN_DELAY)

37
platforms/chibios/atomic_util.h Normal file
View File

@@ -0,0 +1,37 @@
/* Copyright 2021 QMK
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#pragma once
#include <ch.h>
static __inline__ uint8_t __interrupt_disable__(void) {
chSysLock();
return 1;
}
static __inline__ void __interrupt_enable__(const uint8_t *__s) {
chSysUnlock();
__asm__ volatile("" ::: "memory");
(void)__s;
}
#define ATOMIC_BLOCK(type) for (type, __ToDo = __interrupt_disable__(); __ToDo; __ToDo = 0)
#define ATOMIC_FORCEON uint8_t sreg_save __attribute__((__cleanup__(__interrupt_enable__))) = 0
#define ATOMIC_BLOCK_RESTORESTATE _Static_assert(0, "ATOMIC_BLOCK_RESTORESTATE not implemented")
#define ATOMIC_BLOCK_FORCEON ATOMIC_BLOCK(ATOMIC_FORCEON)

71
platforms/chibios/boards/BLACKPILL_STM32_F401/configs/mcuconf.h
View File

@@ -1,5 +1,5 @@
/*
ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
@@ -32,11 +32,15 @@
*/
#define STM32F4xx_MCUCONF
#define STM32F401_MCUCONF
/*
* HAL driver system settings.
*/
#define STM32_NO_INIT FALSE
#define STM32_PVD_ENABLE FALSE
#define STM32_PLS STM32_PLS_LEV0
#define STM32_BKPRAM_ENABLE FALSE
#define STM32_HSI_ENABLED TRUE
#define STM32_LSI_ENABLED TRUE
#define STM32_HSE_ENABLED TRUE
@@ -44,13 +48,13 @@
#define STM32_CLOCK48_REQUIRED TRUE
#define STM32_SW STM32_SW_PLL
#define STM32_PLLSRC STM32_PLLSRC_HSE
#define STM32_PLLM_VALUE 25
#define STM32_PLLN_VALUE 336
#define STM32_PLLP_VALUE 4
#define STM32_PLLQ_VALUE 7
#define STM32_HPRE STM32_HPRE_DIV1
#define STM32_PPRE1 STM32_PPRE1_DIV4
#define STM32_PPRE2 STM32_PPRE2_DIV2
#define STM32_PLLM_VALUE 25
#define STM32_PLLN_VALUE 336
#define STM32_PLLP_VALUE 4
#define STM32_PLLQ_VALUE 7
#define STM32_HPRE STM32_HPRE_DIV1
#define STM32_PPRE1 STM32_PPRE1_DIV4
#define STM32_PPRE2 STM32_PPRE2_DIV2
#define STM32_RTCSEL STM32_RTCSEL_LSI
#define STM32_RTCPRE_VALUE 8
#define STM32_MCO1SEL STM32_MCO1SEL_HSI
@@ -60,9 +64,6 @@
#define STM32_I2SSRC STM32_I2SSRC_CKIN
#define STM32_PLLI2SN_VALUE 192
#define STM32_PLLI2SR_VALUE 5
#define STM32_PVD_ENABLE FALSE
#define STM32_PLS STM32_PLS_LEV0
#define STM32_BKPRAM_ENABLE FALSE
/*
* IRQ system settings.
@@ -82,6 +83,19 @@
#define STM32_IRQ_EXTI21_PRIORITY 15
#define STM32_IRQ_EXTI22_PRIORITY 15
#define STM32_IRQ_TIM1_BRK_TIM9_PRIORITY 7
#define STM32_IRQ_TIM1_UP_TIM10_PRIORITY 7
#define STM32_IRQ_TIM1_TRGCO_TIM11_PRIORITY 7
#define STM32_IRQ_TIM1_CC_PRIORITY 7
#define STM32_IRQ_TIM2_PRIORITY 7
#define STM32_IRQ_TIM3_PRIORITY 7
#define STM32_IRQ_TIM4_PRIORITY 7
#define STM32_IRQ_TIM5_PRIORITY 7
#define STM32_IRQ_USART1_PRIORITY 12
#define STM32_IRQ_USART2_PRIORITY 12
#define STM32_IRQ_USART6_PRIORITY 12
/*
* ADC driver system settings.
*/
@@ -101,14 +115,8 @@
#define STM32_GPT_USE_TIM4 FALSE
#define STM32_GPT_USE_TIM5 FALSE
#define STM32_GPT_USE_TIM9 FALSE
#define STM32_GPT_USE_TIM10 FALSE
#define STM32_GPT_USE_TIM11 FALSE
#define STM32_GPT_TIM1_IRQ_PRIORITY 7
#define STM32_GPT_TIM2_IRQ_PRIORITY 7
#define STM32_GPT_TIM3_IRQ_PRIORITY 7
#define STM32_GPT_TIM4_IRQ_PRIORITY 7
#define STM32_GPT_TIM5_IRQ_PRIORITY 7
#define STM32_GPT_TIM9_IRQ_PRIORITY 7
#define STM32_GPT_TIM11_IRQ_PRIORITY 7
/*
* I2C driver system settings.
@@ -155,29 +163,20 @@
#define STM32_ICU_USE_TIM4 FALSE
#define STM32_ICU_USE_TIM5 FALSE
#define STM32_ICU_USE_TIM9 FALSE
#define STM32_ICU_TIM1_IRQ_PRIORITY 7
#define STM32_ICU_TIM2_IRQ_PRIORITY 7
#define STM32_ICU_TIM3_IRQ_PRIORITY 7
#define STM32_ICU_TIM4_IRQ_PRIORITY 7
#define STM32_ICU_TIM5_IRQ_PRIORITY 7
#define STM32_ICU_TIM9_IRQ_PRIORITY 7
#define STM32_ICU_USE_TIM10 FALSE
#define STM32_ICU_USE_TIM11 FALSE
/*
* PWM driver system settings.
*/
#define STM32_PWM_USE_ADVANCED FALSE
#define STM32_PWM_USE_TIM1 FALSE
#define STM32_PWM_USE_TIM2 FALSE
#define STM32_PWM_USE_TIM3 FALSE
#define STM32_PWM_USE_TIM4 FALSE
#define STM32_PWM_USE_TIM5 FALSE
#define STM32_PWM_USE_TIM9 FALSE
#define STM32_PWM_TIM1_IRQ_PRIORITY 7
#define STM32_PWM_TIM2_IRQ_PRIORITY 7
#define STM32_PWM_TIM3_IRQ_PRIORITY 7
#define STM32_PWM_TIM4_IRQ_PRIORITY 7
#define STM32_PWM_TIM5_IRQ_PRIORITY 7
#define STM32_PWM_TIM9_IRQ_PRIORITY 7
#define STM32_PWM_USE_TIM10 FALSE
#define STM32_PWM_USE_TIM11 FALSE
/*
* SERIAL driver system settings.
@@ -185,9 +184,6 @@
#define STM32_SERIAL_USE_USART1 FALSE
#define STM32_SERIAL_USE_USART2 FALSE
#define STM32_SERIAL_USE_USART6 FALSE
#define STM32_SERIAL_USART1_PRIORITY 12
#define STM32_SERIAL_USART2_PRIORITY 12
#define STM32_SERIAL_USART6_PRIORITY 12
/*
* SPI driver system settings.
@@ -227,9 +223,6 @@
#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
#define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
#define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
#define STM32_UART_USART1_IRQ_PRIORITY 12
#define STM32_UART_USART2_IRQ_PRIORITY 12
#define STM32_UART_USART6_IRQ_PRIORITY 12
#define STM32_UART_USART1_DMA_PRIORITY 0
#define STM32_UART_USART2_DMA_PRIORITY 0
#define STM32_UART_USART6_DMA_PRIORITY 0
@@ -241,9 +234,7 @@
#define STM32_USB_USE_OTG1 TRUE
#define STM32_USB_OTG1_IRQ_PRIORITY 14
#define STM32_USB_OTG1_RX_FIFO_SIZE 512
#define STM32_USB_OTG_THREAD_PRIO NORMALPRIO+1
#define STM32_USB_OTG_THREAD_STACK_SIZE 128
#define STM32_USB_OTGFIFO_FILL_BASEPRI 0
#define STM32_USB_HOST_WAKEUP_DURATION 2
/*
* WDG driver system settings.

65
platforms/chibios/boards/BLACKPILL_STM32_F411/configs/mcuconf.h
View File

@@ -1,5 +1,5 @@
/*
ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
@@ -32,11 +32,15 @@
*/
#define STM32F4xx_MCUCONF
#define STM32F411_MCUCONF
/*
* HAL driver system settings.
*/
#define STM32_NO_INIT FALSE
#define STM32_PVD_ENABLE FALSE
#define STM32_PLS STM32_PLS_LEV0
#define STM32_BKPRAM_ENABLE FALSE
#define STM32_HSI_ENABLED TRUE
#define STM32_LSI_ENABLED TRUE
#define STM32_HSE_ENABLED TRUE
@@ -60,9 +64,6 @@
#define STM32_I2SSRC STM32_I2SSRC_CKIN
#define STM32_PLLI2SN_VALUE 192
#define STM32_PLLI2SR_VALUE 5
#define STM32_PVD_ENABLE FALSE
#define STM32_PLS STM32_PLS_LEV0
#define STM32_BKPRAM_ENABLE FALSE
/*
* IRQ system settings.
@@ -82,6 +83,19 @@
#define STM32_IRQ_EXTI21_PRIORITY 15
#define STM32_IRQ_EXTI22_PRIORITY 15
#define STM32_IRQ_TIM1_BRK_TIM9_PRIORITY 7
#define STM32_IRQ_TIM1_UP_TIM10_PRIORITY 7
#define STM32_IRQ_TIM1_TRGCO_TIM11_PRIORITY 7
#define STM32_IRQ_TIM1_CC_PRIORITY 7
#define STM32_IRQ_TIM2_PRIORITY 7
#define STM32_IRQ_TIM3_PRIORITY 7
#define STM32_IRQ_TIM4_PRIORITY 7
#define STM32_IRQ_TIM5_PRIORITY 7
#define STM32_IRQ_USART1_PRIORITY 12
#define STM32_IRQ_USART2_PRIORITY 12
#define STM32_IRQ_USART6_PRIORITY 12
/*
* ADC driver system settings.
*/
@@ -101,14 +115,8 @@
#define STM32_GPT_USE_TIM4 FALSE
#define STM32_GPT_USE_TIM5 FALSE
#define STM32_GPT_USE_TIM9 FALSE
#define STM32_GPT_USE_TIM10 FALSE
#define STM32_GPT_USE_TIM11 FALSE
#define STM32_GPT_TIM1_IRQ_PRIORITY 7
#define STM32_GPT_TIM2_IRQ_PRIORITY 7
#define STM32_GPT_TIM3_IRQ_PRIORITY 7
#define STM32_GPT_TIM4_IRQ_PRIORITY 7
#define STM32_GPT_TIM5_IRQ_PRIORITY 7
#define STM32_GPT_TIM9_IRQ_PRIORITY 7
#define STM32_GPT_TIM11_IRQ_PRIORITY 7
/*
* I2C driver system settings.
@@ -155,29 +163,28 @@
#define STM32_ICU_USE_TIM4 FALSE
#define STM32_ICU_USE_TIM5 FALSE
#define STM32_ICU_USE_TIM9 FALSE
#define STM32_ICU_TIM1_IRQ_PRIORITY 7
#define STM32_ICU_TIM2_IRQ_PRIORITY 7
#define STM32_ICU_TIM3_IRQ_PRIORITY 7
#define STM32_ICU_TIM4_IRQ_PRIORITY 7
#define STM32_ICU_TIM5_IRQ_PRIORITY 7
#define STM32_ICU_TIM9_IRQ_PRIORITY 7
#define STM32_ICU_USE_TIM10 FALSE
#define STM32_ICU_USE_TIM11 FALSE
/*
* PWM driver system settings.
*/
#define STM32_PWM_USE_ADVANCED FALSE
#define STM32_PWM_USE_TIM1 FALSE
#define STM32_PWM_USE_TIM2 FALSE
#define STM32_PWM_USE_TIM3 FALSE
#define STM32_PWM_USE_TIM4 FALSE
#define STM32_PWM_USE_TIM5 FALSE
#define STM32_PWM_USE_TIM9 FALSE
#define STM32_PWM_TIM1_IRQ_PRIORITY 7
#define STM32_PWM_TIM2_IRQ_PRIORITY 7
#define STM32_PWM_TIM3_IRQ_PRIORITY 7
#define STM32_PWM_TIM4_IRQ_PRIORITY 7
#define STM32_PWM_TIM5_IRQ_PRIORITY 7
#define STM32_PWM_TIM9_IRQ_PRIORITY 7
#define STM32_PWM_USE_TIM10 FALSE
#define STM32_PWM_USE_TIM11 FALSE
/*
* RTC driver system settings.
*/
#define STM32_RTC_PRESA_VALUE 32
#define STM32_RTC_PRESS_VALUE 1024
#define STM32_RTC_CR_INIT 0
#define STM32_RTC_TAMPCR_INIT 0
/*
* SERIAL driver system settings.
@@ -185,9 +192,6 @@
#define STM32_SERIAL_USE_USART1 FALSE
#define STM32_SERIAL_USE_USART2 FALSE
#define STM32_SERIAL_USE_USART6 FALSE
#define STM32_SERIAL_USART1_PRIORITY 12
#define STM32_SERIAL_USART2_PRIORITY 12
#define STM32_SERIAL_USART6_PRIORITY 12
/*
* SPI driver system settings.
@@ -227,9 +231,6 @@
#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
#define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
#define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
#define STM32_UART_USART1_IRQ_PRIORITY 12
#define STM32_UART_USART2_IRQ_PRIORITY 12
#define STM32_UART_USART6_IRQ_PRIORITY 12
#define STM32_UART_USART1_DMA_PRIORITY 0
#define STM32_UART_USART2_DMA_PRIORITY 0
#define STM32_UART_USART6_DMA_PRIORITY 0
@@ -241,9 +242,7 @@
#define STM32_USB_USE_OTG1 TRUE
#define STM32_USB_OTG1_IRQ_PRIORITY 14
#define STM32_USB_OTG1_RX_FIFO_SIZE 512
#define STM32_USB_OTG_THREAD_PRIO NORMALPRIO+1
#define STM32_USB_OTG_THREAD_STACK_SIZE 128
#define STM32_USB_OTGFIFO_FILL_BASEPRI 0
#define STM32_USB_HOST_WAKEUP_DURATION 2
/*
* WDG driver system settings.

9
platforms/chibios/boards/GENERIC_STM32_F405XG/board/board.mk Normal file
View File

@@ -0,0 +1,9 @@
# List of all the board related files.
BOARDSRC = $(CHIBIOS)/os/hal/boards/ST_STM32F4_DISCOVERY/board.c
# Required include directories
BOARDINC = $(CHIBIOS)/os/hal/boards/ST_STM32F4_DISCOVERY
# Shared variables
ALLCSRC += $(BOARDSRC)
ALLINC += $(BOARDINC)

28
platforms/chibios/boards/GENERIC_STM32_F405XG/configs/board.h Normal file
View File

@@ -0,0 +1,28 @@
/* Copyright 2020 Nick Brassel (tzarc)
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <https://www.gnu.org/licenses/>.
*/
#pragma once
#define STM32_HSECLK 12000000
// The following is required to disable the pull-down on PA9, when PA9 is used for the keyboard matrix:
#define BOARD_OTG_NOVBUSSENS
#include_next "board.h"
#undef STM32_HSE_BYPASS
#undef STM32F407xx
#define STM32F405xG
#define STM32F405xx

23
platforms/chibios/boards/GENERIC_STM32_F405XG/configs/config.h Normal file
View File

@@ -0,0 +1,23 @@
/* Copyright 2021 Andrei Purdea
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
/* Address for jumping to bootloader on STM32 chips. */
/* It is chip dependent, the correct number can be looked up by checking against ST's application note AN2606.
*/
#define STM32_BOOTLOADER_ADDRESS 0x1FFF0000
#ifndef EARLY_INIT_PERFORM_BOOTLOADER_JUMP
# define EARLY_INIT_PERFORM_BOOTLOADER_JUMP TRUE
#endif

352
platforms/chibios/boards/GENERIC_STM32_F405XG/configs/mcuconf.h Normal file
View File

@@ -0,0 +1,352 @@
/*
ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
#ifndef MCUCONF_H
#define MCUCONF_H
/*
* STM32F4xx drivers configuration.
* The following settings override the default settings present in
* the various device driver implementation headers.
* Note that the settings for each driver only have effect if the whole
* driver is enabled in halconf.h.
*
* IRQ priorities:
* 15...0 Lowest...Highest.
*
* DMA priorities:
* 0...3 Lowest...Highest.
*/
#define STM32F4xx_MCUCONF
#define STM32F405_MCUCONF
#define STM32F415_MCUCONF
#define STM32F407_MCUCONF
#define STM32F417_MCUCONF
/*
* HAL driver system settings.
*/
#define STM32_NO_INIT FALSE
#define STM32_PVD_ENABLE FALSE
#define STM32_PLS STM32_PLS_LEV0
#define STM32_BKPRAM_ENABLE FALSE
#define STM32_HSI_ENABLED TRUE
#define STM32_LSI_ENABLED TRUE
#define STM32_HSE_ENABLED TRUE
#define STM32_LSE_ENABLED FALSE
#define STM32_CLOCK48_REQUIRED TRUE
#define STM32_SW STM32_SW_PLL
#define STM32_PLLSRC STM32_PLLSRC_HSE
#define STM32_PLLM_VALUE 12
#define STM32_PLLN_VALUE 336
#define STM32_PLLP_VALUE 2
#define STM32_PLLQ_VALUE 7
#define STM32_HPRE STM32_HPRE_DIV1
#define STM32_PPRE1 STM32_PPRE1_DIV4
#define STM32_PPRE2 STM32_PPRE2_DIV2
#define STM32_RTCSEL STM32_RTCSEL_LSI
#define STM32_RTCPRE_VALUE 8
#define STM32_MCO1SEL STM32_MCO1SEL_HSI
#define STM32_MCO1PRE STM32_MCO1PRE_DIV1
#define STM32_MCO2SEL STM32_MCO2SEL_SYSCLK
#define STM32_MCO2PRE STM32_MCO2PRE_DIV5
#define STM32_I2SSRC STM32_I2SSRC_CKIN
#define STM32_PLLI2SN_VALUE 192
#define STM32_PLLI2SR_VALUE 5
/*
* IRQ system settings.
*/
#define STM32_IRQ_EXTI0_PRIORITY 6
#define STM32_IRQ_EXTI1_PRIORITY 6
#define STM32_IRQ_EXTI2_PRIORITY 6
#define STM32_IRQ_EXTI3_PRIORITY 6
#define STM32_IRQ_EXTI4_PRIORITY 6
#define STM32_IRQ_EXTI5_9_PRIORITY 6
#define STM32_IRQ_EXTI10_15_PRIORITY 6
#define STM32_IRQ_EXTI16_PRIORITY 6
#define STM32_IRQ_EXTI17_PRIORITY 15
#define STM32_IRQ_EXTI18_PRIORITY 6
#define STM32_IRQ_EXTI19_PRIORITY 6
#define STM32_IRQ_EXTI20_PRIORITY 6
#define STM32_IRQ_EXTI21_PRIORITY 15
#define STM32_IRQ_EXTI22_PRIORITY 15
/*
* ADC driver system settings.
*/
#define STM32_ADC_ADCPRE ADC_CCR_ADCPRE_DIV4
#define STM32_ADC_USE_ADC1 FALSE
#define STM32_ADC_USE_ADC2 FALSE
#define STM32_ADC_USE_ADC3 FALSE
#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(2, 4)
#define STM32_ADC_ADC2_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
#define STM32_ADC_ADC3_DMA_STREAM STM32_DMA_STREAM_ID(2, 1)
#define STM32_ADC_ADC1_DMA_PRIORITY 2
#define STM32_ADC_ADC2_DMA_PRIORITY 2
#define STM32_ADC_ADC3_DMA_PRIORITY 2
#define STM32_ADC_IRQ_PRIORITY 6
#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 6
#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 6
#define STM32_ADC_ADC3_DMA_IRQ_PRIORITY 6
/*
* CAN driver system settings.
*/
#define STM32_CAN_USE_CAN1 FALSE
#define STM32_CAN_USE_CAN2 FALSE
#define STM32_CAN_CAN1_IRQ_PRIORITY 11
#define STM32_CAN_CAN2_IRQ_PRIORITY 11
/*
* DAC driver system settings.
*/
#define STM32_DAC_DUAL_MODE FALSE
#define STM32_DAC_USE_DAC1_CH1 FALSE
#define STM32_DAC_USE_DAC1_CH2 FALSE
#define STM32_DAC_DAC1_CH1_IRQ_PRIORITY 10
#define STM32_DAC_DAC1_CH2_IRQ_PRIORITY 10
#define STM32_DAC_DAC1_CH1_DMA_PRIORITY 2
#define STM32_DAC_DAC1_CH2_DMA_PRIORITY 2
#define STM32_DAC_DAC1_CH1_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
#define STM32_DAC_DAC1_CH2_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
/*
* GPT driver system settings.
*/
#define STM32_GPT_USE_TIM1 FALSE
#define STM32_GPT_USE_TIM2 FALSE
#define STM32_GPT_USE_TIM3 FALSE
#define STM32_GPT_USE_TIM4 FALSE
#define STM32_GPT_USE_TIM5 FALSE
#define STM32_GPT_USE_TIM6 FALSE
#define STM32_GPT_USE_TIM7 FALSE
#define STM32_GPT_USE_TIM8 FALSE
#define STM32_GPT_USE_TIM9 FALSE
#define STM32_GPT_USE_TIM11 FALSE
#define STM32_GPT_USE_TIM12 FALSE
#define STM32_GPT_USE_TIM14 FALSE
#define STM32_GPT_TIM1_IRQ_PRIORITY 7
#define STM32_GPT_TIM2_IRQ_PRIORITY 7
#define STM32_GPT_TIM3_IRQ_PRIORITY 7
#define STM32_GPT_TIM4_IRQ_PRIORITY 7
#define STM32_GPT_TIM5_IRQ_PRIORITY 7
#define STM32_GPT_TIM6_IRQ_PRIORITY 7
#define STM32_GPT_TIM7_IRQ_PRIORITY 7
#define STM32_GPT_TIM8_IRQ_PRIORITY 7
#define STM32_GPT_TIM9_IRQ_PRIORITY 7
#define STM32_GPT_TIM11_IRQ_PRIORITY 7
#define STM32_GPT_TIM12_IRQ_PRIORITY 7
#define STM32_GPT_TIM14_IRQ_PRIORITY 7
/*
* I2C driver system settings.
*/
#define STM32_I2C_USE_I2C1 FALSE
#define STM32_I2C_USE_I2C2 FALSE
#define STM32_I2C_USE_I2C3 FALSE
#define STM32_I2C_BUSY_TIMEOUT 50
#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0)
#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
#define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
#define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
#define STM32_I2C_I2C1_IRQ_PRIORITY 5
#define STM32_I2C_I2C2_IRQ_PRIORITY 5
#define STM32_I2C_I2C3_IRQ_PRIORITY 5
#define STM32_I2C_I2C1_DMA_PRIORITY 3
#define STM32_I2C_I2C2_DMA_PRIORITY 3
#define STM32_I2C_I2C3_DMA_PRIORITY 3
#define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure")
/*
* I2S driver system settings.
*/
#define STM32_I2S_USE_SPI2 FALSE
#define STM32_I2S_USE_SPI3 FALSE
#define STM32_I2S_SPI2_IRQ_PRIORITY 10
#define STM32_I2S_SPI3_IRQ_PRIORITY 10
#define STM32_I2S_SPI2_DMA_PRIORITY 1
#define STM32_I2S_SPI3_DMA_PRIORITY 1
#define STM32_I2S_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
#define STM32_I2S_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
#define STM32_I2S_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0)
#define STM32_I2S_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
#define STM32_I2S_DMA_ERROR_HOOK(i2sp) osalSysHalt("DMA failure")
/*
* ICU driver system settings.
*/
#define STM32_ICU_USE_TIM1 FALSE
#define STM32_ICU_USE_TIM2 FALSE
#define STM32_ICU_USE_TIM3 FALSE
#define STM32_ICU_USE_TIM4 FALSE
#define STM32_ICU_USE_TIM5 FALSE
#define STM32_ICU_USE_TIM8 FALSE
#define STM32_ICU_USE_TIM9 FALSE
#define STM32_ICU_TIM1_IRQ_PRIORITY 7
#define STM32_ICU_TIM2_IRQ_PRIORITY 7
#define STM32_ICU_TIM3_IRQ_PRIORITY 7
#define STM32_ICU_TIM4_IRQ_PRIORITY 7
#define STM32_ICU_TIM5_IRQ_PRIORITY 7
#define STM32_ICU_TIM8_IRQ_PRIORITY 7
#define STM32_ICU_TIM9_IRQ_PRIORITY 7
/*
* MAC driver system settings.
*/
#define STM32_MAC_TRANSMIT_BUFFERS 2
#define STM32_MAC_RECEIVE_BUFFERS 4
#define STM32_MAC_BUFFERS_SIZE 1522
#define STM32_MAC_PHY_TIMEOUT 100
#define STM32_MAC_ETH1_CHANGE_PHY_STATE TRUE
#define STM32_MAC_ETH1_IRQ_PRIORITY 13
#define STM32_MAC_IP_CHECKSUM_OFFLOAD 0
/*
* PWM driver system settings.
*/
#define STM32_PWM_USE_ADVANCED FALSE
#define STM32_PWM_USE_TIM1 FALSE
#define STM32_PWM_USE_TIM2 FALSE
#define STM32_PWM_USE_TIM3 FALSE
#define STM32_PWM_USE_TIM4 FALSE
#define STM32_PWM_USE_TIM5 FALSE
#define STM32_PWM_USE_TIM8 FALSE
#define STM32_PWM_USE_TIM9 FALSE
#define STM32_PWM_TIM1_IRQ_PRIORITY 7
#define STM32_PWM_TIM2_IRQ_PRIORITY 7
#define STM32_PWM_TIM3_IRQ_PRIORITY 7
#define STM32_PWM_TIM4_IRQ_PRIORITY 7
#define STM32_PWM_TIM5_IRQ_PRIORITY 7
#define STM32_PWM_TIM8_IRQ_PRIORITY 7
#define STM32_PWM_TIM9_IRQ_PRIORITY 7
/*
* RTC driver system settings.
*/
#define STM32_RTC_PRESA_VALUE 32
#define STM32_RTC_PRESS_VALUE 1024
#define STM32_RTC_CR_INIT 0
#define STM32_RTC_TAMPCR_INIT 0
/*
* SDC driver system settings.
*/
#define STM32_SDC_SDIO_DMA_PRIORITY 3
#define STM32_SDC_SDIO_IRQ_PRIORITY 9
#define STM32_SDC_WRITE_TIMEOUT_MS 1000
#define STM32_SDC_READ_TIMEOUT_MS 1000
#define STM32_SDC_CLOCK_ACTIVATION_DELAY 10
#define STM32_SDC_SDIO_UNALIGNED_SUPPORT TRUE
#define STM32_SDC_SDIO_DMA_STREAM STM32_DMA_STREAM_ID(2, 3)
/*
* SERIAL driver system settings.
*/
#define STM32_SERIAL_USE_USART1 FALSE
#define STM32_SERIAL_USE_USART2 FALSE
#define STM32_SERIAL_USE_USART3 FALSE
#define STM32_SERIAL_USE_UART4 FALSE
#define STM32_SERIAL_USE_UART5 FALSE
#define STM32_SERIAL_USE_USART6 FALSE
#define STM32_SERIAL_USART1_PRIORITY 12
#define STM32_SERIAL_USART2_PRIORITY 12
#define STM32_SERIAL_USART3_PRIORITY 12
#define STM32_SERIAL_UART4_PRIORITY 12
#define STM32_SERIAL_UART5_PRIORITY 12
#define STM32_SERIAL_USART6_PRIORITY 12
/*
* SPI driver system settings.
*/
#define STM32_SPI_USE_SPI1 FALSE
#define STM32_SPI_USE_SPI2 FALSE
#define STM32_SPI_USE_SPI3 FALSE
#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0)
#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3)
#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0)
#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
#define STM32_SPI_SPI1_DMA_PRIORITY 1
#define STM32_SPI_SPI2_DMA_PRIORITY 1
#define STM32_SPI_SPI3_DMA_PRIORITY 1
#define STM32_SPI_SPI1_IRQ_PRIORITY 10
#define STM32_SPI_SPI2_IRQ_PRIORITY 10
#define STM32_SPI_SPI3_IRQ_PRIORITY 10
#define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure")
/*
* ST driver system settings.
*/
#define STM32_ST_IRQ_PRIORITY 8
#define STM32_ST_USE_TIMER 2
/*
* UART driver system settings.
*/
#define STM32_UART_USE_USART1 FALSE
#define STM32_UART_USE_USART2 FALSE
#define STM32_UART_USE_USART3 FALSE
#define STM32_UART_USE_UART4 FALSE
#define STM32_UART_USE_UART5 FALSE
#define STM32_UART_USE_USART6 FALSE
#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5)
#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1)
#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
#define STM32_UART_UART4_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
#define STM32_UART_UART4_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
#define STM32_UART_UART5_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0)
#define STM32_UART_UART5_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
#define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
#define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
#define STM32_UART_USART1_IRQ_PRIORITY 12
#define STM32_UART_USART2_IRQ_PRIORITY 12
#define STM32_UART_USART3_IRQ_PRIORITY 12
#define STM32_UART_UART4_IRQ_PRIORITY 12
#define STM32_UART_UART5_IRQ_PRIORITY 12
#define STM32_UART_USART6_IRQ_PRIORITY 12
#define STM32_UART_USART1_DMA_PRIORITY 0
#define STM32_UART_USART2_DMA_PRIORITY 0
#define STM32_UART_USART3_DMA_PRIORITY 0
#define STM32_UART_UART4_DMA_PRIORITY 0
#define STM32_UART_UART5_DMA_PRIORITY 0
#define STM32_UART_USART6_DMA_PRIORITY 0
#define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure")
/*
* USB driver system settings.
*/
#define STM32_USB_USE_OTG1 TRUE
#define STM32_USB_USE_OTG2 FALSE
#define STM32_USB_OTG1_IRQ_PRIORITY 14
#define STM32_USB_OTG2_IRQ_PRIORITY 14
#define STM32_USB_OTG1_RX_FIFO_SIZE 512
#define STM32_USB_OTG2_RX_FIFO_SIZE 1024
#define STM32_USB_HOST_WAKEUP_DURATION 2
/*
* WDG driver system settings.
*/
#define STM32_WDG_USE_IWDG FALSE
#endif /* MCUCONF_H */

3
platforms/chibios/boards/GENERIC_STM32_F407XE/configs/mcuconf.h
View File

@@ -344,9 +344,6 @@
#define STM32_USB_OTG2_RX_FIFO_SIZE 1024
#define STM32_USB_HOST_WAKEUP_DURATION 2
#define STM32_USB_OTG_THREAD_PRIO NORMALPRIO+1
#define STM32_USB_OTG_THREAD_STACK_SIZE 128
/*
* WDG driver system settings.
*/

108
platforms/chibios/boards/GENERIC_STM32_F446XE/configs/mcuconf.h
View File

@@ -1,5 +1,5 @@
/*
ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
@@ -32,11 +32,15 @@
*/
#define STM32F4xx_MCUCONF
#define STM32F446_MCUCONF
/*
* HAL driver system settings.
*/
#define STM32_NO_INIT FALSE
#define STM32_PVD_ENABLE FALSE
#define STM32_PLS STM32_PLS_LEV0
#define STM32_BKPRAM_ENABLE FALSE
#define STM32_HSI_ENABLED FALSE
#define STM32_LSI_ENABLED TRUE
#define STM32_HSE_ENABLED TRUE
@@ -70,9 +74,6 @@
#define STM32_SAI1SEL STM32_SAI2SEL_PLLR
#define STM32_SAI2SEL STM32_SAI2SEL_PLLR
#define STM32_CK48MSEL STM32_CK48MSEL_PLLALT
#define STM32_PVD_ENABLE FALSE
#define STM32_PLS STM32_PLS_LEV0
#define STM32_BKPRAM_ENABLE FALSE
/*
* IRQ system settings.
@@ -92,6 +93,30 @@
#define STM32_IRQ_EXTI21_PRIORITY 15
#define STM32_IRQ_EXTI22_PRIORITY 15
#define STM32_IRQ_TIM1_BRK_TIM9_PRIORITY 7
#define STM32_IRQ_TIM1_UP_TIM10_PRIORITY 7
#define STM32_IRQ_TIM1_TRGCO_TIM11_PRIORITY 7
#define STM32_IRQ_TIM1_CC_PRIORITY 7
#define STM32_IRQ_TIM2_PRIORITY 7
#define STM32_IRQ_TIM3_PRIORITY 7
#define STM32_IRQ_TIM4_PRIORITY 7
#define STM32_IRQ_TIM5_PRIORITY 7
#define STM32_IRQ_TIM6_PRIORITY 7
#define STM32_IRQ_TIM7_PRIORITY 7
#define STM32_IRQ_TIM8_BRK_TIM12_PRIORITY 7
#define STM32_IRQ_TIM8_UP_TIM13_PRIORITY 7
#define STM32_IRQ_TIM8_TRGCO_TIM14_PRIORITY 7
#define STM32_IRQ_TIM8_CC_PRIORITY 7
#define STM32_IRQ_USART1_PRIORITY 12
#define STM32_IRQ_USART2_PRIORITY 12
#define STM32_IRQ_USART3_PRIORITY 12
#define STM32_IRQ_UART4_PRIORITY 12
#define STM32_IRQ_UART5_PRIORITY 12
#define STM32_IRQ_USART6_PRIORITY 12
#define STM32_IRQ_UART7_PRIORITY 12
#define STM32_IRQ_UART8_PRIORITY 12
/*
* ADC driver system settings.
*/
@@ -143,21 +168,11 @@
#define STM32_GPT_USE_TIM7 FALSE
#define STM32_GPT_USE_TIM8 FALSE
#define STM32_GPT_USE_TIM9 FALSE
#define STM32_GPT_USE_TIM10 FALSE
#define STM32_GPT_USE_TIM11 FALSE
#define STM32_GPT_USE_TIM12 FALSE
#define STM32_GPT_USE_TIM13 FALSE
#define STM32_GPT_USE_TIM14 FALSE
#define STM32_GPT_TIM1_IRQ_PRIORITY 7
#define STM32_GPT_TIM2_IRQ_PRIORITY 7
#define STM32_GPT_TIM3_IRQ_PRIORITY 7
#define STM32_GPT_TIM4_IRQ_PRIORITY 7
#define STM32_GPT_TIM5_IRQ_PRIORITY 7
#define STM32_GPT_TIM6_IRQ_PRIORITY 7
#define STM32_GPT_TIM7_IRQ_PRIORITY 7
#define STM32_GPT_TIM8_IRQ_PRIORITY 7
#define STM32_GPT_TIM9_IRQ_PRIORITY 7
#define STM32_GPT_TIM11_IRQ_PRIORITY 7
#define STM32_GPT_TIM12_IRQ_PRIORITY 7
#define STM32_GPT_TIM14_IRQ_PRIORITY 7
/*
* I2C driver system settings.
@@ -205,13 +220,11 @@
#define STM32_ICU_USE_TIM5 FALSE
#define STM32_ICU_USE_TIM8 FALSE
#define STM32_ICU_USE_TIM9 FALSE
#define STM32_ICU_TIM1_IRQ_PRIORITY 7
#define STM32_ICU_TIM2_IRQ_PRIORITY 7
#define STM32_ICU_TIM3_IRQ_PRIORITY 7
#define STM32_ICU_TIM4_IRQ_PRIORITY 7
#define STM32_ICU_TIM5_IRQ_PRIORITY 7
#define STM32_ICU_TIM8_IRQ_PRIORITY 7
#define STM32_ICU_TIM9_IRQ_PRIORITY 7
#define STM32_ICU_USE_TIM10 FALSE
#define STM32_ICU_USE_TIM11 FALSE
#define STM32_ICU_USE_TIM12 FALSE
#define STM32_ICU_USE_TIM13 FALSE
#define STM32_ICU_USE_TIM14 FALSE
/*
* MAC driver system settings.
@@ -227,7 +240,6 @@
/*
* PWM driver system settings.
*/
#define STM32_PWM_USE_ADVANCED FALSE
#define STM32_PWM_USE_TIM1 FALSE
#define STM32_PWM_USE_TIM2 FALSE
#define STM32_PWM_USE_TIM3 FALSE
@@ -235,13 +247,19 @@
#define STM32_PWM_USE_TIM5 FALSE
#define STM32_PWM_USE_TIM8 FALSE
#define STM32_PWM_USE_TIM9 FALSE
#define STM32_PWM_TIM1_IRQ_PRIORITY 7
#define STM32_PWM_TIM2_IRQ_PRIORITY 7
#define STM32_PWM_TIM3_IRQ_PRIORITY 7
#define STM32_PWM_TIM4_IRQ_PRIORITY 7
#define STM32_PWM_TIM5_IRQ_PRIORITY 7
#define STM32_PWM_TIM8_IRQ_PRIORITY 7
#define STM32_PWM_TIM9_IRQ_PRIORITY 7
#define STM32_PWM_USE_TIM10 FALSE
#define STM32_PWM_USE_TIM11 FALSE
#define STM32_PWM_USE_TIM12 FALSE
#define STM32_PWM_USE_TIM13 FALSE
#define STM32_PWM_USE_TIM14 FALSE
/*
* RTC driver system settings.
*/
#define STM32_RTC_PRESA_VALUE 32
#define STM32_RTC_PRESS_VALUE 1024
#define STM32_RTC_CR_INIT 0
#define STM32_RTC_TAMPCR_INIT 0
/*
* SDC driver system settings.
@@ -265,14 +283,6 @@
#define STM32_SERIAL_USE_USART6 FALSE
#define STM32_SERIAL_USE_UART7 FALSE
#define STM32_SERIAL_USE_UART8 FALSE
#define STM32_SERIAL_USART1_PRIORITY 12
#define STM32_SERIAL_USART2_PRIORITY 12
#define STM32_SERIAL_USART3_PRIORITY 12
#define STM32_SERIAL_UART4_PRIORITY 12
#define STM32_SERIAL_UART5_PRIORITY 12
#define STM32_SERIAL_USART6_PRIORITY 12
#define STM32_SERIAL_UART7_PRIORITY 12
#define STM32_SERIAL_UART8_PRIORITY 12
/*
* SPI driver system settings.
@@ -281,6 +291,8 @@
#define STM32_SPI_USE_SPI2 FALSE
#define STM32_SPI_USE_SPI3 FALSE
#define STM32_SPI_USE_SPI4 FALSE
#define STM32_SPI_USE_SPI5 FALSE
#define STM32_SPI_USE_SPI6 FALSE
#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0)
#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3)
#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
@@ -289,14 +301,22 @@
#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
#define STM32_SPI_SPI4_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0)
#define STM32_SPI_SPI4_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 1)
#define STM32_SPI_SPI5_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3)
#define STM32_SPI_SPI5_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 4)
#define STM32_SPI_SPI6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 6)
#define STM32_SPI_SPI6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5)
#define STM32_SPI_SPI1_DMA_PRIORITY 1
#define STM32_SPI_SPI2_DMA_PRIORITY 1
#define STM32_SPI_SPI3_DMA_PRIORITY 1
#define STM32_SPI_SPI4_DMA_PRIORITY 1
#define STM32_SPI_SPI5_DMA_PRIORITY 1
#define STM32_SPI_SPI6_DMA_PRIORITY 1
#define STM32_SPI_SPI1_IRQ_PRIORITY 10
#define STM32_SPI_SPI2_IRQ_PRIORITY 10
#define STM32_SPI_SPI3_IRQ_PRIORITY 10
#define STM32_SPI_SPI4_IRQ_PRIORITY 10
#define STM32_SPI_SPI5_IRQ_PRIORITY 10
#define STM32_SPI_SPI6_IRQ_PRIORITY 10
#define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure")
/*
@@ -326,12 +346,6 @@
#define STM32_UART_UART5_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
#define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
#define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
#define STM32_UART_USART1_IRQ_PRIORITY 12
#define STM32_UART_USART2_IRQ_PRIORITY 12
#define STM32_UART_USART3_IRQ_PRIORITY 12
#define STM32_UART_UART4_IRQ_PRIORITY 12
#define STM32_UART_UART5_IRQ_PRIORITY 12
#define STM32_UART_USART6_IRQ_PRIORITY 12
#define STM32_UART_USART1_DMA_PRIORITY 0
#define STM32_UART_USART2_DMA_PRIORITY 0
#define STM32_UART_USART3_DMA_PRIORITY 0
@@ -349,9 +363,7 @@
#define STM32_USB_OTG2_IRQ_PRIORITY 14
#define STM32_USB_OTG1_RX_FIFO_SIZE 512
#define STM32_USB_OTG2_RX_FIFO_SIZE 1024
#define STM32_USB_OTG_THREAD_PRIO LOWPRIO
#define STM32_USB_OTG_THREAD_STACK_SIZE 128
#define STM32_USB_OTGFIFO_FILL_BASEPRI 0
#define STM32_USB_HOST_WAKEUP_DURATION 2
/*
* WDG driver system settings.

15
platforms/chibios/boards/GENERIC_STM32_G431XB/configs/mcuconf.h
View File

@@ -40,9 +40,24 @@
*/
#define STM32_NO_INIT FALSE
#define STM32_VOS STM32_VOS_RANGE1
#define STM32_PWR_BOOST TRUE
#define STM32_PWR_CR2 (PWR_CR2_PLS_LEV0)
#define STM32_PWR_CR3 (PWR_CR3_EIWF)
#define STM32_PWR_CR4 (0U)
#define STM32_PWR_PUCRA (0U)
#define STM32_PWR_PDCRA (0U)
#define STM32_PWR_PUCRB (0U)
#define STM32_PWR_PDCRB (0U)
#define STM32_PWR_PUCRC (0U)
#define STM32_PWR_PDCRC (0U)
#define STM32_PWR_PUCRD (0U)
#define STM32_PWR_PDCRD (0U)
#define STM32_PWR_PUCRE (0U)
#define STM32_PWR_PDCRE (0U)
#define STM32_PWR_PUCRF (0U)
#define STM32_PWR_PDCRF (0U)
#define STM32_PWR_PUCRG (0U)
#define STM32_PWR_PDCRG (0U)
#define STM32_HSI16_ENABLED TRUE
#define STM32_HSI48_ENABLED TRUE
#define STM32_HSE_ENABLED FALSE

15
platforms/chibios/boards/GENERIC_STM32_G474XE/configs/mcuconf.h
View File

@@ -42,9 +42,24 @@
*/
#define STM32_NO_INIT FALSE
#define STM32_VOS STM32_VOS_RANGE1
#define STM32_PWR_BOOST TRUE
#define STM32_PWR_CR2 (PWR_CR2_PLS_LEV0)
#define STM32_PWR_CR3 (PWR_CR3_EIWF)
#define STM32_PWR_CR4 (0U)
#define STM32_PWR_PUCRA (0U)
#define STM32_PWR_PDCRA (0U)
#define STM32_PWR_PUCRB (0U)
#define STM32_PWR_PDCRB (0U)
#define STM32_PWR_PUCRC (0U)
#define STM32_PWR_PDCRC (0U)
#define STM32_PWR_PUCRD (0U)
#define STM32_PWR_PDCRD (0U)
#define STM32_PWR_PUCRE (0U)
#define STM32_PWR_PDCRE (0U)
#define STM32_PWR_PUCRF (0U)
#define STM32_PWR_PDCRF (0U)
#define STM32_PWR_PUCRG (0U)
#define STM32_PWR_PDCRG (0U)
#define STM32_HSI16_ENABLED TRUE
#define STM32_HSI48_ENABLED TRUE
#define STM32_HSE_ENABLED FALSE

82
platforms/chibios/boards/GENERIC_WB32_F3G71XX/board/board.c Normal file
View File

@@ -0,0 +1,82 @@
/*
Copyright (C) 2021 Westberry Technology (ChangZhou) Corp., Ltd
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/*
* This file has been automatically generated using ChibiStudio board
* generator plugin. Do not edit manually.
*/
#include "hal.h"
/*===========================================================================*/
/* Driver local definitions. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver exported variables. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver local variables and types. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver local functions. */
/*===========================================================================*/
static void wb32_gpio_init(void) {
#if WB32_HAS_GPIOA
rccEnableAPB1(RCC_APB1ENR_GPIOAEN);
#endif
#if WB32_HAS_GPIOB
rccEnableAPB1(RCC_APB1ENR_GPIOBEN);
#endif
#if WB32_HAS_GPIOC
rccEnableAPB1(RCC_APB1ENR_GPIOCEN);
#endif
#if WB32_HAS_GPIOD
rccEnableAPB1(RCC_APB1ENR_GPIODEN);
#endif
}
/*===========================================================================*/
/* Driver interrupt handlers. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver exported functions. */
/*===========================================================================*/
/*
* Early initialization code.
* This initialization must be performed just after stack setup and before
* any other initialization.
*/
void __early_init(void) {
wb32_clock_init();
wb32_gpio_init();
}
/**
* @brief Board-specific initialization code.
* @note You can add your board-specific code here.
*/
void boardInit(void) {
}

56
platforms/chibios/boards/GENERIC_WB32_F3G71XX/board/board.h Normal file
View File

@@ -0,0 +1,56 @@
#pragma once
/*
Copyright (C) 2021 Westberry Technology (ChangZhou) Corp., Ltd
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/*
* This file has been automatically generated using ChibiStudio board
* generator plugin. Do not edit manually.
*/
#ifndef BOARD_H
#define BOARD_H
/*===========================================================================*/
/* Driver constants. */
/*===========================================================================*/
/*
* Setup board.
*/
/*
* Board identifier.
*/
#define WB32F3G71x9
#if !defined(WB32F3G71xx)
#define WB32F3G71xx
#endif
/*===========================================================================*/
/* External declarations. */
/*===========================================================================*/
#if !defined(_FROM_ASM_)
#ifdef __cplusplus
extern "C" {
#endif
void boardInit(void);
#ifdef __cplusplus
}
#endif
#endif /* _FROM_ASM_ */
#endif /* BOARD_H */

9
platforms/chibios/boards/GENERIC_WB32_F3G71XX/board/board.mk Normal file
View File

@@ -0,0 +1,9 @@
# List of all the board related files.
BOARDSRC = $(BOARD_PATH)/board/board.c
# Required include directories
BOARDINC = $(BOARD_PATH)/board
# Shared variables
ALLCSRC += $(BOARDSRC)
ALLINC += $(BOARDINC)

12
platforms/chibios/boards/GENERIC_WB32_F3G71XX/configs/bootloader_defs.h Normal file
View File

@@ -0,0 +1,12 @@
/* Address for jumping to bootloader on WB32 chips. */
/* It is chip dependent, the correct number can be looked up here:
* http://www.westberrytech.com/down/mcu/data/WB32F3G71xx_rm.pdf
*/
#ifndef WB32_BOOTLOADER_ADDRESS
# undef STM32_BOOTLOADER_ADDRESS
# define WB32_BOOTLOADER_ADDRESS 0x1FFFE000
# define STM32_BOOTLOADER_ADDRESS WB32_BOOTLOADER_ADDRESS
#else
# undef STM32_BOOTLOADER_ADDRESS
# define STM32_BOOTLOADER_ADDRESS WB32_BOOTLOADER_ADDRESS
#endif

26
platforms/chibios/boards/GENERIC_WB32_F3G71XX/configs/chconf.h Normal file
View File

@@ -0,0 +1,26 @@
/* Copyright 2020 QMK
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
/*
* This file was auto-generated by:
* `qmk chibios-confmigrate -i platforms/chibios/boards/GENERIC_WB32_F3G71XX/configs/chconf.h -r platforms/chibios/boards/common/configs/chconf.h`
*/
#pragma once
#define CH_CFG_ST_TIMEDELTA 0
#include_next <chconf.h>

20
platforms/chibios/boards/GENERIC_WB32_F3G71XX/configs/config.h Normal file
View File

@@ -0,0 +1,20 @@
/* Copyright (C) 2021 Westberry Technology (ChangZhou) Corp., Ltd
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <https://www.gnu.org/licenses/>.
*/
#pragma once
#ifndef EARLY_INIT_PERFORM_BOOTLOADER_JUMP
# define EARLY_INIT_PERFORM_BOOTLOADER_JUMP TRUE
#endif

168
platforms/chibios/boards/GENERIC_WB32_F3G71XX/configs/mcuconf.h Normal file
View File

@@ -0,0 +1,168 @@
/*
Copyright (C) 2021 Westberry Technology (ChangZhou) Corp., Ltd
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
#ifndef MCUCONF_H
#define MCUCONF_H
#define WB32F3G71xx_MCUCONF TRUE
/*
* WB32F3G71 drivers configuration.
* The following settings override the default settings present in
* the various device driver implementation headers.
* Note that the settings for each driver only have effect if the whole
* driver is enabled in halconf.h.
*
* IRQ priorities:
* 15...0 Lowest...Highest.
*
*/
/**
* @name Internal clock sources
* @{
*/
#define WB32_HSECLK 12000000
#define WB32_LSECLK 32768
/*
* HAL driver system settings.
*/
#define WB32_NO_INIT FALSE
#define WB32_MHSI_ENABLED TRUE
#define WB32_FHSI_ENABLED FALSE
#define WB32_LSI_ENABLED FALSE
#define WB32_HSE_ENABLED TRUE
#define WB32_LSE_ENABLED FALSE
#define WB32_PLL_ENABLED TRUE
#define WB32_MAINCLKSRC WB32_MAINCLKSRC_PLL
#define WB32_PLLSRC WB32_PLLSRC_HSE
#define WB32_PLLDIV_VALUE 2
#define WB32_PLLMUL_VALUE 12 //The allowed range is 12,16,20,24.
#define WB32_HPRE 1
#define WB32_PPRE1 1
#define WB32_PPRE2 1
#define WB32_USBPRE WB32_USBPRE_DIV1P5
/*
* EXTI driver system settings.
*/
#define WB32_IRQ_EXTI0_PRIORITY 6
#define WB32_IRQ_EXTI1_PRIORITY 6
#define WB32_IRQ_EXTI2_PRIORITY 6
#define WB32_IRQ_EXTI3_PRIORITY 6
#define WB32_IRQ_EXTI4_PRIORITY 6
#define WB32_IRQ_EXTI5_9_PRIORITY 6
#define WB32_IRQ_EXTI10_15_PRIORITY 6
#define WB32_IRQ_EXTI16_PRIORITY 6
#define WB32_IRQ_EXTI17_PRIORITY 6
#define WB32_IRQ_EXTI18_PRIORITY 6
#define WB32_IRQ_EXTI19_PRIORITY 6
/*
* GPT driver system settings.
*/
#define WB32_TIM_MAX_CHANNELS 4
#define WB32_GPT_USE_TIM1 FALSE
#define WB32_GPT_USE_TIM2 FALSE
#define WB32_GPT_USE_TIM3 FALSE
#define WB32_GPT_USE_TIM4 FALSE
#define WB32_GPT_TIM1_IRQ_PRIORITY 7
#define WB32_GPT_TIM2_IRQ_PRIORITY 7
#define WB32_GPT_TIM3_IRQ_PRIORITY 7
#define WB32_GPT_TIM4_IRQ_PRIORITY 7
/*
* ICU driver system settings.
*/
#define WB32_ICU_USE_TIM1 FALSE
#define WB32_ICU_USE_TIM2 FALSE
#define WB32_ICU_USE_TIM3 FALSE
#define WB32_ICU_USE_TIM4 FALSE
#define WB32_ICU_TIM1_IRQ_PRIORITY 7
#define WB32_ICU_TIM2_IRQ_PRIORITY 7
#define WB32_ICU_TIM3_IRQ_PRIORITY 7
#define WB32_ICU_TIM4_IRQ_PRIORITY 7
/*
* PWM driver system settings.
*/
#define WB32_PWM_USE_ADVANCED FALSE
#define WB32_PWM_USE_TIM1 FALSE
#define WB32_PWM_USE_TIM2 FALSE
#define WB32_PWM_USE_TIM3 FALSE
#define WB32_PWM_USE_TIM4 FALSE
#define WB32_PWM_TIM1_IRQ_PRIORITY 7
#define WB32_PWM_TIM2_IRQ_PRIORITY 7
#define WB32_PWM_TIM3_IRQ_PRIORITY 7
#define WB32_PWM_TIM4_IRQ_PRIORITY 7
/*
* I2C driver system settings.
*/
#define WB32_I2C_USE_I2C1 FALSE
#define WB32_I2C_USE_I2C2 FALSE
#define WB32_I2C_BUSY_TIMEOUT 50
#define WB32_I2C_I2C1_IRQ_PRIORITY 5
#define WB32_I2C_I2C2_IRQ_PRIORITY 5
/*
* SERIAL driver system settings.
*/
#define WB32_SERIAL_USE_UART1 FALSE
#define WB32_SERIAL_USE_UART2 FALSE
#define WB32_SERIAL_USE_UART3 FALSE
#define WB32_SERIAL_USART1_PRIORITY 12
#define WB32_SERIAL_USART2_PRIORITY 12
#define WB32_SERIAL_USART3_PRIORITY 12
/*
* SPI driver system settings.
*/
#define WB32_SPI_USE_QSPI FALSE
#define WB32_SPI_USE_SPIM2 FALSE
#define WB32_SPI_USE_SPIS1 FALSE
#define WB32_SPI_USE_SPIS2 FALSE
#define WB32_SPI_QSPI_IRQ_PRIORITY 10
#define WB32_SPI_SPIM2_IRQ_PRIORITY 10
#define WB32_SPI_SPIS1_IRQ_PRIORITY 10
#define WB32_SPI_SPIS2_IRQ_PRIORITY 10
/*
* ST driver system settings.
*/
#define WB32_ST_IRQ_PRIORITY 8
#define WB32_ST_USE_TIMER 2
/*
* UART driver system settings.
*/
#define WB32_UART_USE_UART1 FALSE
#define WB32_UART_USE_UART2 FALSE
#define WB32_UART_USE_UART3 FALSE
#define WB32_UART_UART1_IRQ_PRIORITY 12
#define WB32_UART_UART2_IRQ_PRIORITY 12
#define WB32_UART_UART3_IRQ_PRIORITY 12
/*
* USB driver system settings.
*/
#define WB32_USB_USE_USB1 TRUE
#define WB32_USB_USB1_IRQ_PRIORITY 13
#define WB32_USB_HOST_WAKEUP_DURATION 10
#endif /* MCUCONF_H */

2
platforms/chibios/boards/QMK_PROTON_C/configs/chconf.h
View File

@@ -40,7 +40,7 @@
/**
* @brief System time counter resolution.
* @note Allowed values are 16 or 32 bits.
* @note Allowed values are 16, 32 or 64 bits.
*/
#if !defined(CH_CFG_ST_RESOLUTION)
#define CH_CFG_ST_RESOLUTION 32

9
platforms/chibios/boards/QMK_PROTON_C/configs/config.h
View File

@@ -18,3 +18,12 @@
#ifndef EARLY_INIT_PERFORM_BOOTLOADER_JUMP
# define EARLY_INIT_PERFORM_BOOTLOADER_JUMP TRUE
#endif
#ifdef CONVERT_TO_PROTON_C
# ifndef I2C1_SDA_PIN
# define I2C1_SDA_PIN D1
# endif
# ifndef I2C1_SCL_PIN
# define I2C1_SCL_PIN D0
# endif
#endif

9
platforms/chibios/boards/SIPEED_LONGAN_NANO/board/board.mk Normal file
View File

@@ -0,0 +1,9 @@
# List of all the board related files.
BOARDSRC = ${CHIBIOS_CONTRIB}/os/hal/boards/SIPEED_LONGAN_NANO/board.c
# Required include directories
BOARDINC = ${CHIBIOS_CONTRIB}/os/hal/boards/SIPEED_LONGAN_NANO
# Shared variables
ALLCSRC += $(BOARDSRC)
ALLINC += $(BOARDINC)

23
platforms/chibios/boards/SIPEED_LONGAN_NANO/configs/chconf.h Normal file
View File

@@ -0,0 +1,23 @@
/* Copyright 2021 QMK
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
/* To compile the ChibiOS syscall stubs with picolibc
* the _reent struct has to be defined. */
#if !defined(_FROM_ASM_) && defined(USE_PICOLIBC)
struct _reent;
#endif
#include_next <chconf.h>

302
platforms/chibios/boards/SIPEED_LONGAN_NANO/configs/mcuconf.h Normal file
View File

@@ -0,0 +1,302 @@
/*
ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
ChibiOS - Copyright (C) 2021 Stefan Kerkmann
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
#pragma once
#define GD32VF103_MCUCONF
#define GD32VF103CB
/*
* GD32VF103 drivers configuration.
* The following settings override the default settings present in
* the various device driver implementation headers.
* Note that the settings for each driver only have effect if the whole
* driver is enabled in halconf.h.
*
* IRQ priorities:
* 0...15 Lowest...Highest.
*
* DMA priorities:
* 0...3 Lowest...Highest.
*/
/*
* HAL driver system settings.
*/
#if defined(OVERCLOCK_120MHZ)
/* (8MHz / 2) * 30 = 120MHz Sysclock */
#define GD32_ALLOW_120MHZ_SYSCLK
#define GD32_PLLMF_VALUE 30
#define GD32_USBFSPSC GD32_USBFSPSC_DIV2P5
#else
/* (8MHz / 2) * 24 = 96MHz Sysclock */
#define GD32_PLLMF_VALUE 24
#define GD32_USBFSPSC GD32_USBFSPSC_DIV2
#endif
#define GD32_NO_INIT FALSE
#define GD32_IRC8M_ENABLED TRUE
#define GD32_IRC40K_ENABLED FALSE
#define GD32_HXTAL_ENABLED TRUE
#define GD32_LXTAL_ENABLED FALSE
#define GD32_SCS GD32_SCS_PLL
#define GD32_PLLSEL GD32_PLLSEL_PREDV0
#define GD32_PREDV0SEL GD32_PREDV0SEL_HXTAL
#define GD32_PREDV0_VALUE 2
#define GD32_PREDV1_VALUE 2
#define GD32_PLL1MF_VALUE 14
#define GD32_PLL2MF_VALUE 13
#define GD32_AHBPSC GD32_AHBPSC_DIV1
#define GD32_APB1PSC GD32_APB1PSC_DIV2
#define GD32_APB2PSC GD32_APB2PSC_DIV1
#define GD32_ADCPSC GD32_ADCPSC_DIV16
#define GD32_USB_CLOCK_REQUIRED TRUE
#define GD32_I2S_CLOCK_REQUIRED FALSE
#define GD32_CKOUT0SEL GD32_CKOUT0SEL_NOCLOCK
#define GD32_RTCSRC GD32_RTCSRC_NOCLOCK
#define GD32_PVD_ENABLE FALSE
#define GD32_LVDT GD32_LVDT_LEV0
/*
* ECLIC system settings.
*/
#define ECLIC_TRIGGER_DEFAULT ECLIC_POSTIVE_EDGE_TRIGGER
#define ECLIC_DMA_TRIGGER ECLIC_TRIGGER_DEFAULT
/*
* IRQ system settings.
*/
#define GD32_IRQ_EXTI0_PRIORITY 6
#define GD32_IRQ_EXTI1_PRIORITY 6
#define GD32_IRQ_EXTI2_PRIORITY 6
#define GD32_IRQ_EXTI3_PRIORITY 6
#define GD32_IRQ_EXTI4_PRIORITY 6
#define GD32_IRQ_EXTI5_9_PRIORITY 6
#define GD32_IRQ_EXTI10_15_PRIORITY 6
#define GD32_IRQ_EXTI0_TRIGGER ECLIC_TRIGGER_DEFAULT
#define GD32_IRQ_EXTI1_TRIGGER ECLIC_TRIGGER_DEFAULT
#define GD32_IRQ_EXTI2_TRIGGER ECLIC_TRIGGER_DEFAULT
#define GD32_IRQ_EXTI3_TRIGGER ECLIC_TRIGGER_DEFAULT
#define GD32_IRQ_EXTI4_TRIGGER ECLIC_TRIGGER_DEFAULT
#define GD32_IRQ_EXTI5_9_TRIGGER ECLIC_TRIGGER_DEFAULT
#define GD32_IRQ_EXTI10_15_TRIGGER ECLIC_TRIGGER_DEFAULT
/*
* ADC driver system settings.
*/
#define GD32_ADC_USE_ADC0 FALSE
#define GD32_ADC_ADC0_DMA_PRIORITY 2
#define GD32_ADC_ADC0_IRQ_PRIORITY 6
/*
* CAN driver system settings.
*/
#define GD32_CAN_USE_CAN0 FALSE
#define GD32_CAN_CAN0_IRQ_PRIORITY 11
#define GD32_CAN_USE_CAN1 FALSE
#define GD32_CAN_CAN1_IRQ_PRIORITY 11
#define GD32_CAN_CAN0_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
#define GD32_CAN_CAN1_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
/*
* CRC driver system settings.
*/
#define GD32_CRC_USE_CRC0 FALSE
#define GD32_CRC_CRC0_DMA_IRQ_PRIORITY 14
#define GD32_CRC_CRC0_DMA_PRIORITY 2
#define GD32_CRC_CRC0_DMA_STREAM GD32_DMA_STREAM_ID(0, 0)
#define CRC_USE_DMA FALSE
#define CRCSW_USE_CRC1 FALSE
#define CRCSW_CRC32_TABLE FALSE
#define CRCSW_CRC16_TABLE FALSE
#define CRCSW_PROGRAMMABLE FALSE
/*
* DAC driver system settings.
*/
#define GD32_DAC_USE_DAC_CH1 FALSE
#define GD32_DAC_USE_DAC_CH2 FALSE
/*
* GPT driver system settings.
*/
#define GD32_GPT_USE_TIM0 FALSE
#define GD32_GPT_USE_TIM1 FALSE
#define GD32_GPT_USE_TIM2 FALSE
#define GD32_GPT_USE_TIM3 FALSE
#define GD32_GPT_USE_TIM4 FALSE
#define GD32_GPT_TIM0_IRQ_PRIORITY 7
#define GD32_GPT_TIM1_IRQ_PRIORITY 7
#define GD32_GPT_TIM2_IRQ_PRIORITY 7
#define GD32_GPT_TIM3_IRQ_PRIORITY 7
#define GD32_GPT_TIM4_IRQ_PRIORITY 7
#define GD32_GPT_TIM0_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
#define GD32_GPT_TIM1_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
#define GD32_GPT_TIM2_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
#define GD32_GPT_TIM3_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
#define GD32_GPT_TIM4_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
#define GD32_GPT_TIM5_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
#define GD32_GPT_TIM6_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
/*
* I2S driver system settings.
*/
#define GD32_I2S_USE_SPI1 FALSE
#define GD32_I2S_USE_SPI2 FALSE
#define GD32_I2S_SPI1_IRQ_PRIORITY 10
#define GD32_I2S_SPI2_IRQ_PRIORITY 10
#define GD32_I2S_SPI1_DMA_PRIORITY 1
#define GD32_I2S_SPI2_DMA_PRIORITY 1
#define GD32_I2S_DMA_ERROR_HOOK(i2sp) osalSysHalt("DMA failure")
/*
* I2C driver system settings.
*/
#define GD32_I2C_USE_I2C0 FALSE
#define GD32_I2C_USE_I2C1 FALSE
#define GD32_I2C_BUSY_TIMEOUT 50
#define GD32_I2C_I2C0_IRQ_PRIORITY 10
#define GD32_I2C_I2C1_IRQ_PRIORITY 5
#define GD32_I2C_I2C0_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
#define GD32_I2C_I2C1_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
#define GD32_I2C_I2C0_DMA_PRIORITY 2
#define GD32_I2C_I2C1_DMA_PRIORITY 2
#define GD32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure")
/*
* ICU driver system settings.
*/
#define GD32_ICU_USE_TIM0 FALSE
#define GD32_ICU_USE_TIM1 FALSE
#define GD32_ICU_USE_TIM2 FALSE
#define GD32_ICU_USE_TIM3 FALSE
#define GD32_ICU_USE_TIM4 FALSE
#define GD32_ICU_TIM0_IRQ_PRIORITY 7
#define GD32_ICU_TIM1_IRQ_PRIORITY 7
#define GD32_ICU_TIM2_IRQ_PRIORITY 7
#define GD32_ICU_TIM3_IRQ_PRIORITY 7
#define GD32_ICU_TIM4_IRQ_PRIORITY 7
#define GD32_ICU_TIM0_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
#define GD32_ICU_TIM1_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
#define GD32_ICU_TIM2_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
#define GD32_ICU_TIM3_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
#define GD32_ICU_TIM4_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
/*
* PWM driver system settings.
*/
#define GD32_PWM_USE_ADVANCED FALSE
#define GD32_PWM_USE_TIM0 FALSE
#define GD32_PWM_USE_TIM1 FALSE
#define GD32_PWM_USE_TIM2 FALSE
#define GD32_PWM_USE_TIM3 FALSE
#define GD32_PWM_USE_TIM4 FALSE
#define GD32_PWM_TIM0_IRQ_PRIORITY 10
#define GD32_PWM_TIM1_IRQ_PRIORITY 10
#define GD32_PWM_TIM2_IRQ_PRIORITY 10
#define GD32_PWM_TIM3_IRQ_PRIORITY 10
#define GD32_PWM_TIM4_IRQ_PRIORITY 10
#define GD32_PWM_TIM0_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
#define GD32_PWM_TIM1_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
#define GD32_PWM_TIM2_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
#define GD32_PWM_TIM3_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
#define GD32_PWM_TIM4_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
/*
* RTC driver system settings.
*/
#define GD32_RTC_IRQ_PRIORITY 15
#define GD32_RTC_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
/*
* SERIAL driver system settings.
*/
#define GD32_SERIAL_USE_USART0 FALSE
#define GD32_SERIAL_USE_USART1 FALSE
#define GD32_SERIAL_USE_USART2 FALSE
#define GD32_SERIAL_USE_UART3 FALSE
#define GD32_SERIAL_USE_UART4 FALSE
#define GD32_SERIAL_USART0_PRIORITY 10
#define GD32_SERIAL_USART1_PRIORITY 10
#define GD32_SERIAL_USART2_PRIORITY 10
#define GD32_SERIAL_UART3_PRIORITY 10
#define GD32_SERIAL_UART4_PRIORITY 10
#define GD32_SERIAL_USART0_TRIGGER ECLIC_TRIGGER_DEFAULT
#define GD32_SERIAL_USART1_TRIGGER ECLIC_TRIGGER_DEFAULT
#define GD32_SERIAL_USART2_TRIGGER ECLIC_TRIGGER_DEFAULT
#define GD32_SERIAL_UART3_TRIGGER ECLIC_TRIGGER_DEFAULT
#define GD32_SERIAL_UART4_TRIGGER ECLIC_TRIGGER_DEFAULT
/*
* SPI driver system settings.
*/
#define GD32_SPI_USE_SPI0 FALSE
#define GD32_SPI_USE_SPI1 FALSE
#define GD32_SPI_USE_SPI2 FALSE
#define GD32_SPI_SPI0_DMA_PRIORITY 1
#define GD32_SPI_SPI1_DMA_PRIORITY 1
#define GD32_SPI_SPI2_DMA_PRIORITY 1
#define GD32_SPI_SPI0_IRQ_PRIORITY 10
#define GD32_SPI_SPI1_IRQ_PRIORITY 10
#define GD32_SPI_SPI2_IRQ_PRIORITY 10
#define GD32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure")
/*
* ST driver system settings.
*/
#define GD32_ST_IRQ_PRIORITY 10
#define GD32_ST_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
#define GD32_ST_USE_TIMER 1
/*
* UART driver system settings.
*/
#define GD32_UART_USE_USART0 FALSE
#define GD32_UART_USE_USART1 FALSE
#define GD32_UART_USE_USART2 FALSE
#define GD32_UART_USE_UART3 FALSE
#define GD32_UART_USE_UART4 FALSE
#define GD32_UART_USART0_IRQ_PRIORITY 10
#define GD32_UART_USART1_IRQ_PRIORITY 10
#define GD32_UART_USART2_IRQ_PRIORITY 10
#define GD32_UART_UART3_IRQ_PRIORITY 10
#define GD32_UART_UART4_IRQ_PRIORITY 10
#define GD32_UART_USART0_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
#define GD32_UART_USART1_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
#define GD32_UART_USART2_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
#define GD32_UART_UART3_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
#define GD32_UART_UART4_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
#define GD32_UART_USART0_DMA_PRIORITY 3
#define GD32_UART_USART1_DMA_PRIORITY 3
#define GD32_UART_USART2_DMA_PRIORITY 3
#define GD32_UART_UART3_DMA_PRIORITY 3
#define GD32_UART_UART4_DMA_PRIORITY 3
#define GD32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure")
/*
* USB driver system settings.
*/
#define GD32_USB_USE_USBFS TRUE
#define GD32_USB_USBFS_IRQ_PRIORITY 10
#define GD32_USB_USBFS_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
#define GD32_USB_USBFS_RX_FIFO_SIZE 256
/*
* WDG driver system settings.
*/
#define GD32_WDG_USE_FWDGT FALSE

2
platforms/chibios/boards/common/configs/chconf.h
View File

@@ -40,7 +40,7 @@
/**
* @brief System time counter resolution.
* @note Allowed values are 16 or 32 bits.
* @note Allowed values are 16, 32 or 64 bits.
*/
#if !defined(CH_CFG_ST_RESOLUTION)
#define CH_CFG_ST_RESOLUTION 32

85
platforms/chibios/boards/common/ld/STM32F401xC.ld Normal file
View File

@@ -0,0 +1,85 @@
/*
ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/*
* STM32F401xC memory setup.
*/
MEMORY
{
flash0 (rx) : org = 0x08000000, len = 16k /* Sector 0 - Init code as ROM bootloader assumes application starts here */
flash1 (rx) : org = 0x08004000, len = 16k /* Sector 1 - Emulated eeprom */
flash2 (rx) : org = 0x08008000, len = 256k - 32k /* Sector 2..6 - Rest of firmware */
flash3 (rx) : org = 0x00000000, len = 0
flash4 (rx) : org = 0x00000000, len = 0
flash5 (rx) : org = 0x00000000, len = 0
flash6 (rx) : org = 0x00000000, len = 0
flash7 (rx) : org = 0x00000000, len = 0
ram0 (wx) : org = 0x20000000, len = 64k
ram1 (wx) : org = 0x00000000, len = 0
ram2 (wx) : org = 0x00000000, len = 0
ram3 (wx) : org = 0x00000000, len = 0
ram4 (wx) : org = 0x00000000, len = 0
ram5 (wx) : org = 0x00000000, len = 0
ram6 (wx) : org = 0x00000000, len = 0
ram7 (wx) : org = 0x00000000, len = 0
}
/* For each data/text section two region are defined, a virtual region
and a load region (_LMA suffix).*/
/* Flash region to be used for exception vectors.*/
REGION_ALIAS("VECTORS_FLASH", flash0);
REGION_ALIAS("VECTORS_FLASH_LMA", flash0);
/* Flash region to be used for constructors and destructors.*/
REGION_ALIAS("XTORS_FLASH", flash2);
REGION_ALIAS("XTORS_FLASH_LMA", flash2);
/* Flash region to be used for code text.*/
REGION_ALIAS("TEXT_FLASH", flash2);
REGION_ALIAS("TEXT_FLASH_LMA", flash2);
/* Flash region to be used for read only data.*/
REGION_ALIAS("RODATA_FLASH", flash2);
REGION_ALIAS("RODATA_FLASH_LMA", flash2);
/* Flash region to be used for various.*/
REGION_ALIAS("VARIOUS_FLASH", flash2);
REGION_ALIAS("VARIOUS_FLASH_LMA", flash2);
/* Flash region to be used for RAM(n) initialization data.*/
REGION_ALIAS("RAM_INIT_FLASH_LMA", flash2);
/* RAM region to be used for Main stack. This stack accommodates the processing
of all exceptions and interrupts.*/
REGION_ALIAS("MAIN_STACK_RAM", ram0);
/* RAM region to be used for the process stack. This is the stack used by
the main() function.*/
REGION_ALIAS("PROCESS_STACK_RAM", ram0);
/* RAM region to be used for data segment.*/
REGION_ALIAS("DATA_RAM", ram0);
REGION_ALIAS("DATA_RAM_LMA", flash2);
/* RAM region to be used for BSS segment.*/
REGION_ALIAS("BSS_RAM", ram0);
/* RAM region to be used for the default heap.*/
REGION_ALIAS("HEAP_RAM", ram0);
/* Generic rules inclusion.*/
INCLUDE rules.ld

85
platforms/chibios/boards/common/ld/STM32F401xE.ld Normal file
View File

@@ -0,0 +1,85 @@
/*
ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/*
* STM32F401xE memory setup.
*/
MEMORY
{
flash0 (rx) : org = 0x08000000, len = 16k /* Sector 0 - Init code as ROM bootloader assumes application starts here */
flash1 (rx) : org = 0x08004000, len = 16k /* Sector 1 - Emulated eeprom */
flash2 (rx) : org = 0x08008000, len = 512k - 32k /* Sector 2..7 - Rest of firmware */
flash3 (rx) : org = 0x00000000, len = 0
flash4 (rx) : org = 0x00000000, len = 0
flash5 (rx) : org = 0x00000000, len = 0
flash6 (rx) : org = 0x00000000, len = 0
flash7 (rx) : org = 0x00000000, len = 0
ram0 (wx) : org = 0x20000000, len = 96k
ram1 (wx) : org = 0x00000000, len = 0
ram2 (wx) : org = 0x00000000, len = 0
ram3 (wx) : org = 0x00000000, len = 0
ram4 (wx) : org = 0x00000000, len = 0
ram5 (wx) : org = 0x00000000, len = 0
ram6 (wx) : org = 0x00000000, len = 0
ram7 (wx) : org = 0x00000000, len = 0
}
/* For each data/text section two region are defined, a virtual region
and a load region (_LMA suffix).*/
/* Flash region to be used for exception vectors.*/
REGION_ALIAS("VECTORS_FLASH", flash0);
REGION_ALIAS("VECTORS_FLASH_LMA", flash0);
/* Flash region to be used for constructors and destructors.*/
REGION_ALIAS("XTORS_FLASH", flash2);
REGION_ALIAS("XTORS_FLASH_LMA", flash2);
/* Flash region to be used for code text.*/
REGION_ALIAS("TEXT_FLASH", flash2);
REGION_ALIAS("TEXT_FLASH_LMA", flash2);
/* Flash region to be used for read only data.*/
REGION_ALIAS("RODATA_FLASH", flash2);
REGION_ALIAS("RODATA_FLASH_LMA", flash2);
/* Flash region to be used for various.*/
REGION_ALIAS("VARIOUS_FLASH", flash2);
REGION_ALIAS("VARIOUS_FLASH_LMA", flash2);
/* Flash region to be used for RAM(n) initialization data.*/
REGION_ALIAS("RAM_INIT_FLASH_LMA", flash2);
/* RAM region to be used for Main stack. This stack accommodates the processing
of all exceptions and interrupts.*/
REGION_ALIAS("MAIN_STACK_RAM", ram0);
/* RAM region to be used for the process stack. This is the stack used by
the main() function.*/
REGION_ALIAS("PROCESS_STACK_RAM", ram0);
/* RAM region to be used for data segment.*/
REGION_ALIAS("DATA_RAM", ram0);
REGION_ALIAS("DATA_RAM_LMA", flash2);
/* RAM region to be used for BSS segment.*/
REGION_ALIAS("BSS_RAM", ram0);
/* RAM region to be used for the default heap.*/
REGION_ALIAS("HEAP_RAM", ram0);
/* Generic rules inclusion.*/
INCLUDE rules.ld

86
platforms/chibios/boards/common/ld/STM32F405xG.ld Normal file
View File

@@ -0,0 +1,86 @@
/*
ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/*
* STM32F405xG memory setup.
* Note: Use of ram1 and ram2 is mutually exclusive with use of ram0.
*/
MEMORY
{
flash0 (rx) : org = 0x08000000, len = 16k /* Sector 0 - Init code as ROM bootloader assumes application starts here */
flash1 (rx) : org = 0x08004000, len = 16k /* Sector 1 - Emulated eeprom */
flash2 (rx) : org = 0x08008000, len = 1M - 32k /* Sector 2..6 - Rest of firmware */
flash3 (rx) : org = 0x00000000, len = 0
flash4 (rx) : org = 0x00000000, len = 0
flash5 (rx) : org = 0x00000000, len = 0
flash6 (rx) : org = 0x00000000, len = 0
flash7 (rx) : org = 0x00000000, len = 0
ram0 (wx) : org = 0x20000000, len = 128k /* SRAM1 + SRAM2 */
ram1 (wx) : org = 0x20000000, len = 112k /* SRAM1 */
ram2 (wx) : org = 0x2001C000, len = 16k /* SRAM2 */
ram3 (wx) : org = 0x00000000, len = 0
ram4 (wx) : org = 0x10000000, len = 64k /* CCM SRAM */
ram5 (wx) : org = 0x40024000, len = 4k /* BCKP SRAM */
ram6 (wx) : org = 0x00000000, len = 0
ram7 (wx) : org = 0x00000000, len = 0
}
/* For each data/text section two region are defined, a virtual region
and a load region (_LMA suffix).*/
/* Flash region to be used for exception vectors.*/
REGION_ALIAS("VECTORS_FLASH", flash0);
REGION_ALIAS("VECTORS_FLASH_LMA", flash0);
/* Flash region to be used for constructors and destructors.*/
REGION_ALIAS("XTORS_FLASH", flash2);
REGION_ALIAS("XTORS_FLASH_LMA", flash2);
/* Flash region to be used for code text.*/
REGION_ALIAS("TEXT_FLASH", flash2);
REGION_ALIAS("TEXT_FLASH_LMA", flash2);
/* Flash region to be used for read only data.*/
REGION_ALIAS("RODATA_FLASH", flash2);
REGION_ALIAS("RODATA_FLASH_LMA", flash2);
/* Flash region to be used for various.*/
REGION_ALIAS("VARIOUS_FLASH", flash2);
REGION_ALIAS("VARIOUS_FLASH_LMA", flash2);
/* Flash region to be used for RAM(n) initialization data.*/
REGION_ALIAS("RAM_INIT_FLASH_LMA", flash2);
/* RAM region to be used for Main stack. This stack accommodates the processing
of all exceptions and interrupts.*/
REGION_ALIAS("MAIN_STACK_RAM", ram0);
/* RAM region to be used for the process stack. This is the stack used by
the main() function.*/
REGION_ALIAS("PROCESS_STACK_RAM", ram0);
/* RAM region to be used for data segment.*/
REGION_ALIAS("DATA_RAM", ram0);
REGION_ALIAS("DATA_RAM_LMA", flash2);
/* RAM region to be used for BSS segment.*/
REGION_ALIAS("BSS_RAM", ram0);
/* RAM region to be used for the default heap.*/
REGION_ALIAS("HEAP_RAM", ram0);
/* Generic rules inclusion.*/
INCLUDE rules.ld

85
platforms/chibios/boards/common/ld/STM32F411xE.ld Normal file
View File

@@ -0,0 +1,85 @@
/*
ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/*
* STM32F411xE memory setup.
*/
MEMORY
{
flash0 (rx) : org = 0x08000000, len = 16k /* Sector 0 - Init code as ROM bootloader assumes application starts here */
flash1 (rx) : org = 0x08004000, len = 16k /* Sector 1 - Emulated eeprom */
flash2 (rx) : org = 0x08008000, len = 512k - 32k /* Sector 2..7 - Rest of firmware */
flash3 (rx) : org = 0x00000000, len = 0
flash4 (rx) : org = 0x00000000, len = 0
flash5 (rx) : org = 0x00000000, len = 0
flash6 (rx) : org = 0x00000000, len = 0
flash7 (rx) : org = 0x00000000, len = 0
ram0 (wx) : org = 0x20000000, len = 128k
ram1 (wx) : org = 0x00000000, len = 0
ram2 (wx) : org = 0x00000000, len = 0
ram3 (wx) : org = 0x00000000, len = 0
ram4 (wx) : org = 0x00000000, len = 0
ram5 (wx) : org = 0x00000000, len = 0
ram6 (wx) : org = 0x00000000, len = 0
ram7 (wx) : org = 0x00000000, len = 0
}
/* For each data/text section two region are defined, a virtual region
and a load region (_LMA suffix).*/
/* Flash region to be used for exception vectors.*/
REGION_ALIAS("VECTORS_FLASH", flash0);
REGION_ALIAS("VECTORS_FLASH_LMA", flash0);
/* Flash region to be used for constructors and destructors.*/
REGION_ALIAS("XTORS_FLASH", flash2);
REGION_ALIAS("XTORS_FLASH_LMA", flash2);
/* Flash region to be used for code text.*/
REGION_ALIAS("TEXT_FLASH", flash2);
REGION_ALIAS("TEXT_FLASH_LMA", flash2);
/* Flash region to be used for read only data.*/
REGION_ALIAS("RODATA_FLASH", flash2);
REGION_ALIAS("RODATA_FLASH_LMA", flash2);
/* Flash region to be used for various.*/
REGION_ALIAS("VARIOUS_FLASH", flash2);
REGION_ALIAS("VARIOUS_FLASH_LMA", flash2);
/* Flash region to be used for RAM(n) initialization data.*/
REGION_ALIAS("RAM_INIT_FLASH_LMA", flash2);
/* RAM region to be used for Main stack. This stack accommodates the processing
of all exceptions and interrupts.*/
REGION_ALIAS("MAIN_STACK_RAM", ram0);
/* RAM region to be used for the process stack. This is the stack used by
the main() function.*/
REGION_ALIAS("PROCESS_STACK_RAM", ram0);
/* RAM region to be used for data segment.*/
REGION_ALIAS("DATA_RAM", ram0);
REGION_ALIAS("DATA_RAM_LMA", flash2);
/* RAM region to be used for BSS segment.*/
REGION_ALIAS("BSS_RAM", ram0);
/* RAM region to be used for the default heap.*/
REGION_ALIAS("HEAP_RAM", ram0);
/* Generic rules inclusion.*/
INCLUDE rules.ld

145
platforms/chibios/bootloader.c Normal file
View File

@@ -0,0 +1,145 @@
#include "bootloader.h"
#include <ch.h>
#include <hal.h>
#include "wait.h"
/* This code should be checked whether it runs correctly on platforms */
#define SYMVAL(sym) (uint32_t)(((uint8_t *)&(sym)) - ((uint8_t *)0))
#define BOOTLOADER_MAGIC 0xDEADBEEF
#define MAGIC_ADDR (unsigned long *)(SYMVAL(__ram0_end__) - 4)
#ifndef STM32_BOOTLOADER_DUAL_BANK
# define STM32_BOOTLOADER_DUAL_BANK FALSE
#endif
#ifdef BOOTLOADER_TINYUF2
# define DBL_TAP_MAGIC 0xf01669ef // From tinyuf2's board_api.h
// defined by linker script
extern uint32_t _board_dfu_dbl_tap[];
# define DBL_TAP_REG _board_dfu_dbl_tap[0]
void bootloader_jump(void) {
DBL_TAP_REG = DBL_TAP_MAGIC;
NVIC_SystemReset();
}
void enter_bootloader_mode_if_requested(void) { /* not needed, no two-stage reset */
}
#elif STM32_BOOTLOADER_DUAL_BANK
// Need pin definitions
# include "config_common.h"
# ifndef STM32_BOOTLOADER_DUAL_BANK_GPIO
# error "No STM32_BOOTLOADER_DUAL_BANK_GPIO defined, don't know which pin to toggle"
# endif
# ifndef STM32_BOOTLOADER_DUAL_BANK_POLARITY
# define STM32_BOOTLOADER_DUAL_BANK_POLARITY 0
# endif
# ifndef STM32_BOOTLOADER_DUAL_BANK_DELAY
# define STM32_BOOTLOADER_DUAL_BANK_DELAY 100000
# endif
extern uint32_t __ram0_end__;
__attribute__((weak)) void bootloader_jump(void) {
// For STM32 MCUs with dual-bank flash, and we're incapable of jumping to the bootloader. The first valid flash
// bank is executed unconditionally after a reset, so it doesn't enter DFU unless BOOT0 is high. Instead, we do
// it with hardware...in this case, we pull a GPIO high/low depending on the configuration, connects 3.3V to
// BOOT0's RC charging circuit, lets it charge the capacitor, and issue a system reset. See the QMK discord
// #hardware channel pins for an example circuit.
palSetPadMode(PAL_PORT(STM32_BOOTLOADER_DUAL_BANK_GPIO), PAL_PAD(STM32_BOOTLOADER_DUAL_BANK_GPIO), PAL_MODE_OUTPUT_PUSHPULL);
# if STM32_BOOTLOADER_DUAL_BANK_POLARITY
palSetPad(PAL_PORT(STM32_BOOTLOADER_DUAL_BANK_GPIO), PAL_PAD(STM32_BOOTLOADER_DUAL_BANK_GPIO));
# else
palClearPad(PAL_PORT(STM32_BOOTLOADER_DUAL_BANK_GPIO), PAL_PAD(STM32_BOOTLOADER_DUAL_BANK_GPIO));
# endif
// Wait for a while for the capacitor to charge
wait_ms(100);
// Issue a system reset to get the ROM bootloader to execute, with BOOT0 high
NVIC_SystemReset();
}
void enter_bootloader_mode_if_requested(void) {} // not needed at all, but if anybody attempts to invoke it....
#elif defined(STM32_BOOTLOADER_ADDRESS) // STM32_BOOTLOADER_DUAL_BANK
extern uint32_t __ram0_end__;
__attribute__((weak)) void bootloader_jump(void) {
*MAGIC_ADDR = BOOTLOADER_MAGIC; // set magic flag => reset handler will jump into boot loader
NVIC_SystemReset();
}
void enter_bootloader_mode_if_requested(void) {
unsigned long *check = MAGIC_ADDR;
if (*check == BOOTLOADER_MAGIC) {
*check = 0;
__set_CONTROL(0);
__set_MSP(*(__IO uint32_t *)STM32_BOOTLOADER_ADDRESS);
__enable_irq();
typedef void (*BootJump_t)(void);
BootJump_t boot_jump = *(BootJump_t *)(STM32_BOOTLOADER_ADDRESS + 4);
boot_jump();
while (1)
;
}
}
#elif defined(GD32VF103)
# define DBGMCU_KEY_UNLOCK 0x4B5A6978
# define DBGMCU_CMD_RESET 0x1
__IO uint32_t *DBGMCU_KEY = (uint32_t *)DBGMCU_BASE + 0x0CU;
__IO uint32_t *DBGMCU_CMD = (uint32_t *)DBGMCU_BASE + 0x08U;
__attribute__((weak)) void bootloader_jump(void) {
/* The MTIMER unit of the GD32VF103 doesn't have the MSFRST
* register to generate a software reset request.
* BUT instead two undocumented registers in the debug peripheral
* that allow issueing a software reset. WHO would need the MSFRST
* register anyway? Source:
* https://github.com/esmil/gd32vf103inator/blob/master/include/gd32vf103/dbg.h */
*DBGMCU_KEY = DBGMCU_KEY_UNLOCK;
*DBGMCU_CMD = DBGMCU_CMD_RESET;
}
void enter_bootloader_mode_if_requested(void) { /* Jumping to bootloader is not possible from user code. */
}
#elif defined(KL2x) || defined(K20x) || defined(MK66F18) || defined(MIMXRT1062) // STM32_BOOTLOADER_DUAL_BANK // STM32_BOOTLOADER_ADDRESS
/* Kinetis */
# if defined(BOOTLOADER_KIIBOHD)
/* Kiibohd Bootloader (MCHCK and Infinity KB) */
# define SCB_AIRCR_VECTKEY_WRITEMAGIC 0x05FA0000
const uint8_t sys_reset_to_loader_magic[] = "\xff\x00\x7fRESET TO LOADER\x7f\x00\xff";
__attribute__((weak)) void bootloader_jump(void) {
void *volatile vbat = (void *)VBAT;
__builtin_memcpy(vbat, (const void *)sys_reset_to_loader_magic, sizeof(sys_reset_to_loader_magic));
// request reset
SCB->AIRCR = SCB_AIRCR_VECTKEY_WRITEMAGIC | SCB_AIRCR_SYSRESETREQ_Msk;
}
# else /* defined(BOOTLOADER_KIIBOHD) */
/* Default for Kinetis - expecting an ARM Teensy */
# include "wait.h"
__attribute__((weak)) void bootloader_jump(void) {
wait_ms(100);
__BKPT(0);
}
# endif /* defined(BOOTLOADER_KIIBOHD) */
#else /* neither STM32 nor KINETIS */
__attribute__((weak)) void bootloader_jump(void) {}
#endif

90
platforms/chibios/chibios_config.h Normal file
View File

@@ -0,0 +1,90 @@
/* Copyright 2019
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#pragma once
#ifndef USB_VBUS_PIN
# define SPLIT_USB_DETECT // Force this on when dedicated pin is not used
#endif
// STM32 compatibility
#if defined(MCU_STM32)
# define CPU_CLOCK STM32_SYSCLK
# if defined(STM32F1XX)
# define USE_GPIOV1
# define PAL_MODE_ALTERNATE_OPENDRAIN PAL_MODE_STM32_ALTERNATE_OPENDRAIN
# define PAL_MODE_ALTERNATE_PUSHPULL PAL_MODE_STM32_ALTERNATE_PUSHPULL
# else
# define PAL_OUTPUT_TYPE_OPENDRAIN PAL_STM32_OTYPE_OPENDRAIN
# define PAL_OUTPUT_TYPE_PUSHPULL PAL_STM32_OTYPE_PUSHPULL
# define PAL_OUTPUT_SPEED_HIGHEST PAL_STM32_OSPEED_HIGHEST
# define PAL_PUPDR_FLOATING PAL_STM32_PUPDR_FLOATING
# endif
# if defined(STM32F1XX) || defined(STM32F2XX) || defined(STM32F4XX) || defined(STM32L1XX)
# define USE_I2CV1
# endif
#endif
// GD32 compatibility
#if defined(MCU_GD32V)
# define CPU_CLOCK GD32_SYSCLK
# if defined(GD32VF103)
# define USE_GPIOV1
# define USE_I2CV1
# define PAL_MODE_ALTERNATE_OPENDRAIN PAL_MODE_GD32_ALTERNATE_OPENDRAIN
# define PAL_MODE_ALTERNATE_PUSHPULL PAL_MODE_GD32_ALTERNATE_PUSHPULL
# endif
#endif
// WB32 compatibility
#if defined(MCU_WB32)
# define CPU_CLOCK WB32_MAINCLK
# if defined(WB32F3G71xx)
# define PAL_OUTPUT_TYPE_OPENDRAIN PAL_WB32_OTYPE_OPENDRAIN
# define PAL_OUTPUT_TYPE_PUSHPULL PAL_WB32_OTYPE_PUSHPULL
# define PAL_OUTPUT_SPEED_HIGHEST PAL_WB32_OSPEED_HIGH
# define PAL_PUPDR_FLOATING PAL_WB32_PUPDR_FLOATING
# endif
#endif
#if defined(GD32VF103)
/* This chip has the same API as STM32F103, but uses different names for literally the same thing.
* As of 4.7.2021 QMK is tailored to use STM32 defines/names, for compatibility sake
* we just redefine the GD32 names. */
# include "gd32v_compatibility.h"
#endif
// teensy compatibility
#if defined(MCU_KINETIS)
# define CPU_CLOCK KINETIS_SYSCLK_FREQUENCY
# if defined(K20x) || defined(KL2x)
# define USE_I2CV1
# define USE_I2CV1_CONTRIB // for some reason a bunch of ChibiOS-Contrib boards only have clock_speed
# define USE_GPIOV1
# endif
#endif
#if defined(HT32)
# define CPU_CLOCK HT32_CK_SYS_FREQUENCY
# define PAL_MODE_ALTERNATE PAL_HT32_MODE_AF
# define PAL_OUTPUT_TYPE_OPENDRAIN (PAL_HT32_MODE_OD | PAL_HT32_MODE_DIR)
# define PAL_OUTPUT_TYPE_PUSHPULL PAL_HT32_MODE_DIR
# define PAL_OUTPUT_SPEED_HIGHEST 0
#endif

10
platforms/chibios/drivers/analog.c
View File

@@ -38,7 +38,7 @@
// Otherwise assume V3
#if defined(STM32F0XX) || defined(STM32L0XX)
# define USE_ADCV1
#elif defined(STM32F1XX) || defined(STM32F2XX) || defined(STM32F4XX)
#elif defined(STM32F1XX) || defined(STM32F2XX) || defined(STM32F4XX) || defined(GD32VF103)
# define USE_ADCV2
#endif
@@ -75,7 +75,7 @@
/* User configurable ADC options */
#ifndef ADC_COUNT
# if defined(STM32F0XX) || defined(STM32F1XX) || defined(STM32F4XX)
# if defined(STM32F0XX) || defined(STM32F1XX) || defined(STM32F4XX) || defined(GD32VF103)
# define ADC_COUNT 1
# elif defined(STM32F3XX)
# define ADC_COUNT 4
@@ -122,8 +122,8 @@ static ADCConversionGroup adcConversionGroup = {
.cfgr1 = ADC_CFGR1_CONT | ADC_RESOLUTION,
.smpr = ADC_SAMPLING_RATE,
#elif defined(USE_ADCV2)
# if !defined(STM32F1XX)
.cr2 = ADC_CR2_SWSTART, // F103 seem very unhappy with, F401 seems very unhappy without...
# if !defined(STM32F1XX) && !defined(GD32VF103)
.cr2 = ADC_CR2_SWSTART, // F103 seem very unhappy with, F401 seems very unhappy without...
# endif
.smpr2 = ADC_SMPR2_SMP_AN0(ADC_SAMPLING_RATE) | ADC_SMPR2_SMP_AN1(ADC_SAMPLING_RATE) | ADC_SMPR2_SMP_AN2(ADC_SAMPLING_RATE) | ADC_SMPR2_SMP_AN3(ADC_SAMPLING_RATE) | ADC_SMPR2_SMP_AN4(ADC_SAMPLING_RATE) | ADC_SMPR2_SMP_AN5(ADC_SAMPLING_RATE) | ADC_SMPR2_SMP_AN6(ADC_SAMPLING_RATE) | ADC_SMPR2_SMP_AN7(ADC_SAMPLING_RATE) | ADC_SMPR2_SMP_AN8(ADC_SAMPLING_RATE) | ADC_SMPR2_SMP_AN9(ADC_SAMPLING_RATE),
.smpr1 = ADC_SMPR1_SMP_AN10(ADC_SAMPLING_RATE) | ADC_SMPR1_SMP_AN11(ADC_SAMPLING_RATE) | ADC_SMPR1_SMP_AN12(ADC_SAMPLING_RATE) | ADC_SMPR1_SMP_AN13(ADC_SAMPLING_RATE) | ADC_SMPR1_SMP_AN14(ADC_SAMPLING_RATE) | ADC_SMPR1_SMP_AN15(ADC_SAMPLING_RATE),
@@ -220,7 +220,7 @@ __attribute__((weak)) adc_mux pinToMux(pin_t pin) {
case F9: return TO_MUX( ADC_CHANNEL_IN7, 2 );
case F10: return TO_MUX( ADC_CHANNEL_IN8, 2 );
# endif
#elif defined(STM32F1XX)
#elif defined(STM32F1XX) || defined(GD32VF103)
case A0: return TO_MUX( ADC_CHANNEL_IN0, 0 );
case A1: return TO_MUX( ADC_CHANNEL_IN1, 0 );
case A2: return TO_MUX( ADC_CHANNEL_IN2, 0 );

126
platforms/chibios/drivers/audio_dac.h Normal file
View File

@@ -0,0 +1,126 @@
/* Copyright 2019 Jack Humbert
* Copyright 2020 JohSchneider
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#pragma once
#ifndef A4
# define A4 PAL_LINE(GPIOA, 4)
#endif
#ifndef A5
# define A5 PAL_LINE(GPIOA, 5)
#endif
/**
* Size of the dac_buffer arrays. All must be the same size.
*/
#define AUDIO_DAC_BUFFER_SIZE 256U
/**
* Highest value allowed sample value.
* since the DAC is limited to 12 bit, the absolute max is 0xfff = 4095U;
* lower values adjust the peak-voltage aka volume down.
* adjusting this value has only an effect on a sample-buffer whose values are
* are NOT pregenerated - see square-wave
*/
#ifndef AUDIO_DAC_SAMPLE_MAX
# define AUDIO_DAC_SAMPLE_MAX 4095U
#endif
#if !defined(AUDIO_DAC_SAMPLE_RATE) && !defined(AUDIO_MAX_SIMULTANEOUS_TONES) && !defined(AUDIO_DAC_QUALITY_VERY_LOW) && !defined(AUDIO_DAC_QUALITY_LOW) && !defined(AUDIO_DAC_QUALITY_HIGH) && !defined(AUDIO_DAC_QUALITY_VERY_HIGH)
# define AUDIO_DAC_QUALITY_SANE_MINIMUM
#endif
/**
* These presets allow you to quickly switch between quality settings for
* the DAC. The sample rate and maximum number of simultaneous tones roughly
* has an inverse relationship - slightly higher sample rates may be possible.
*
* NOTE: a high sample-rate results in a higher cpu-load, which might lead to
* (audible) discontinuities and/or starve other processes of cpu-time
* (like RGB-led back-lighting, ...)
*/
#ifdef AUDIO_DAC_QUALITY_VERY_LOW
# define AUDIO_DAC_SAMPLE_RATE 11025U
# define AUDIO_MAX_SIMULTANEOUS_TONES 8
#endif
#ifdef AUDIO_DAC_QUALITY_LOW
# define AUDIO_DAC_SAMPLE_RATE 22050U
# define AUDIO_MAX_SIMULTANEOUS_TONES 4
#endif
#ifdef AUDIO_DAC_QUALITY_HIGH
# define AUDIO_DAC_SAMPLE_RATE 44100U
# define AUDIO_MAX_SIMULTANEOUS_TONES 2
#endif
#ifdef AUDIO_DAC_QUALITY_VERY_HIGH
# define AUDIO_DAC_SAMPLE_RATE 88200U
# define AUDIO_MAX_SIMULTANEOUS_TONES 1
#endif
#ifdef AUDIO_DAC_QUALITY_SANE_MINIMUM
/* a sane-minimum config: with a trade-off between cpu-load and tone-range
*
* the (currently) highest defined note is NOTE_B8 with 7902Hz; if we now
* aim for an even even multiple of the buffer-size, we end up with:
* ( roundUptoPow2(highest note / AUDIO_DAC_BUFFER_SIZE) * nyquist-rate * AUDIO_DAC_BUFFER_SIZE)
* 7902/256 = 30.867 * 2 * 256 ~= 16384
* which works out (but the 'scope shows some sampling artifacts with lower harmonics :-P)
*/
# define AUDIO_DAC_SAMPLE_RATE 16384U
# define AUDIO_MAX_SIMULTANEOUS_TONES 8
#endif
/**
* Effective bit-rate of the DAC. 44.1khz is the standard for most audio - any
* lower will sacrifice perceptible audio quality. Any higher will limit the
* number of simultaneous tones. In most situations, a tenth (1/10) of the
* sample rate is where notes become unbearable.
*/
#ifndef AUDIO_DAC_SAMPLE_RATE
# define AUDIO_DAC_SAMPLE_RATE 44100U
#endif
/**
* The number of tones that can be played simultaneously. If too high a value
* is used here, the keyboard will freeze and glitch-out when that many tones
* are being played.
*/
#ifndef AUDIO_MAX_SIMULTANEOUS_TONES
# define AUDIO_MAX_SIMULTANEOUS_TONES 2
#endif
/**
* The default value of the DAC when not playing anything. Certain hardware
* setups may require a high (AUDIO_DAC_SAMPLE_MAX) or low (0) value here.
* Since multiple added sine waves tend to oscillate around the midpoint,
* and possibly never/rarely reach either 0 of MAX, 1/2 MAX can be a
* reasonable default value.
*/
#ifndef AUDIO_DAC_OFF_VALUE
# define AUDIO_DAC_OFF_VALUE AUDIO_DAC_SAMPLE_MAX / 2
#endif
#if AUDIO_DAC_OFF_VALUE > AUDIO_DAC_SAMPLE_MAX
# error "AUDIO_DAC: OFF_VALUE may not be larger than SAMPLE_MAX"
#endif
/**
*user overridable sample generation/processing
*/
uint16_t dac_value_generate(void);

335
platforms/chibios/drivers/audio_dac_additive.c Normal file
View File

@@ -0,0 +1,335 @@
/* Copyright 2016-2019 Jack Humbert
* Copyright 2020 JohSchneider
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#include "audio.h"
#include <ch.h>
#include <hal.h>
/*
Audio Driver: DAC
which utilizes the dac unit many STM32 are equipped with, to output a modulated waveform from samples stored in the dac_buffer_* array who are passed to the hardware through DMA
it is also possible to have a custom sample-LUT by implementing/overriding 'dac_value_generate'
this driver allows for multiple simultaneous tones to be played through one single channel by doing additive wave-synthesis
*/
#if !defined(AUDIO_PIN)
# error "Audio feature enabled, but no suitable pin selected as AUDIO_PIN - see docs/feature_audio under 'ARM (DAC additive)' for available options."
#endif
#if defined(AUDIO_PIN_ALT) && !defined(AUDIO_PIN_ALT_AS_NEGATIVE)
# pragma message "Audio feature: AUDIO_PIN_ALT set, but not AUDIO_PIN_ALT_AS_NEGATIVE - pin will be left unused; audio might still work though."
#endif
#if !defined(AUDIO_PIN_ALT)
// no ALT pin defined is valid, but the c-ifs below need some value set
# define AUDIO_PIN_ALT PAL_NOLINE
#endif
#if !defined(AUDIO_DAC_SAMPLE_WAVEFORM_SINE) && !defined(AUDIO_DAC_SAMPLE_WAVEFORM_TRIANGLE) && !defined(AUDIO_DAC_SAMPLE_WAVEFORM_SQUARE) && !defined(AUDIO_DAC_SAMPLE_WAVEFORM_TRAPEZOID)
# define AUDIO_DAC_SAMPLE_WAVEFORM_SINE
#endif
#ifdef AUDIO_DAC_SAMPLE_WAVEFORM_SINE
/* one full sine wave over [0,2*pi], but shifted up one amplitude and left pi/4; for the samples to start at 0
*/
static const dacsample_t dac_buffer_sine[AUDIO_DAC_BUFFER_SIZE] = {
// 256 values, max 4095
0x0, 0x1, 0x2, 0x6, 0xa, 0xf, 0x16, 0x1e, 0x27, 0x32, 0x3d, 0x4a, 0x58, 0x67, 0x78, 0x89, 0x9c, 0xb0, 0xc5, 0xdb, 0xf2, 0x10a, 0x123, 0x13e, 0x159, 0x175, 0x193, 0x1b1, 0x1d1, 0x1f1, 0x212, 0x235, 0x258, 0x27c, 0x2a0, 0x2c6, 0x2ed, 0x314, 0x33c, 0x365, 0x38e, 0x3b8, 0x3e3, 0x40e, 0x43a, 0x467, 0x494, 0x4c2, 0x4f0, 0x51f, 0x54e, 0x57d, 0x5ad, 0x5dd, 0x60e, 0x63f, 0x670, 0x6a1, 0x6d3, 0x705, 0x737, 0x769, 0x79b, 0x7cd, 0x800, 0x832, 0x864, 0x896, 0x8c8, 0x8fa, 0x92c, 0x95e, 0x98f, 0x9c0, 0x9f1, 0xa22, 0xa52, 0xa82, 0xab1, 0xae0, 0xb0f, 0xb3d, 0xb6b, 0xb98, 0xbc5, 0xbf1, 0xc1c, 0xc47, 0xc71, 0xc9a, 0xcc3, 0xceb, 0xd12, 0xd39, 0xd5f, 0xd83, 0xda7, 0xdca, 0xded, 0xe0e, 0xe2e, 0xe4e, 0xe6c, 0xe8a, 0xea6, 0xec1, 0xedc, 0xef5, 0xf0d, 0xf24, 0xf3a, 0xf4f, 0xf63, 0xf76, 0xf87, 0xf98, 0xfa7, 0xfb5, 0xfc2, 0xfcd, 0xfd8, 0xfe1, 0xfe9, 0xff0, 0xff5, 0xff9, 0xffd, 0xffe,
0xfff, 0xffe, 0xffd, 0xff9, 0xff5, 0xff0, 0xfe9, 0xfe1, 0xfd8, 0xfcd, 0xfc2, 0xfb5, 0xfa7, 0xf98, 0xf87, 0xf76, 0xf63, 0xf4f, 0xf3a, 0xf24, 0xf0d, 0xef5, 0xedc, 0xec1, 0xea6, 0xe8a, 0xe6c, 0xe4e, 0xe2e, 0xe0e, 0xded, 0xdca, 0xda7, 0xd83, 0xd5f, 0xd39, 0xd12, 0xceb, 0xcc3, 0xc9a, 0xc71, 0xc47, 0xc1c, 0xbf1, 0xbc5, 0xb98, 0xb6b, 0xb3d, 0xb0f, 0xae0, 0xab1, 0xa82, 0xa52, 0xa22, 0x9f1, 0x9c0, 0x98f, 0x95e, 0x92c, 0x8fa, 0x8c8, 0x896, 0x864, 0x832, 0x800, 0x7cd, 0x79b, 0x769, 0x737, 0x705, 0x6d3, 0x6a1, 0x670, 0x63f, 0x60e, 0x5dd, 0x5ad, 0x57d, 0x54e, 0x51f, 0x4f0, 0x4c2, 0x494, 0x467, 0x43a, 0x40e, 0x3e3, 0x3b8, 0x38e, 0x365, 0x33c, 0x314, 0x2ed, 0x2c6, 0x2a0, 0x27c, 0x258, 0x235, 0x212, 0x1f1, 0x1d1, 0x1b1, 0x193, 0x175, 0x159, 0x13e, 0x123, 0x10a, 0xf2, 0xdb, 0xc5, 0xb0, 0x9c, 0x89, 0x78, 0x67, 0x58, 0x4a, 0x3d, 0x32, 0x27, 0x1e, 0x16, 0xf, 0xa, 0x6, 0x2, 0x1};
#endif // AUDIO_DAC_SAMPLE_WAVEFORM_SINE
#ifdef AUDIO_DAC_SAMPLE_WAVEFORM_TRIANGLE
static const dacsample_t dac_buffer_triangle[AUDIO_DAC_BUFFER_SIZE] = {
// 256 values, max 4095
0x0, 0x20, 0x40, 0x60, 0x80, 0xa0, 0xc0, 0xe0, 0x100, 0x120, 0x140, 0x160, 0x180, 0x1a0, 0x1c0, 0x1e0, 0x200, 0x220, 0x240, 0x260, 0x280, 0x2a0, 0x2c0, 0x2e0, 0x300, 0x320, 0x340, 0x360, 0x380, 0x3a0, 0x3c0, 0x3e0, 0x400, 0x420, 0x440, 0x460, 0x480, 0x4a0, 0x4c0, 0x4e0, 0x500, 0x520, 0x540, 0x560, 0x580, 0x5a0, 0x5c0, 0x5e0, 0x600, 0x620, 0x640, 0x660, 0x680, 0x6a0, 0x6c0, 0x6e0, 0x700, 0x720, 0x740, 0x760, 0x780, 0x7a0, 0x7c0, 0x7e0, 0x800, 0x81f, 0x83f, 0x85f, 0x87f, 0x89f, 0x8bf, 0x8df, 0x8ff, 0x91f, 0x93f, 0x95f, 0x97f, 0x99f, 0x9bf, 0x9df, 0x9ff, 0xa1f, 0xa3f, 0xa5f, 0xa7f, 0xa9f, 0xabf, 0xadf, 0xaff, 0xb1f, 0xb3f, 0xb5f, 0xb7f, 0xb9f, 0xbbf, 0xbdf, 0xbff, 0xc1f, 0xc3f, 0xc5f, 0xc7f, 0xc9f, 0xcbf, 0xcdf, 0xcff, 0xd1f, 0xd3f, 0xd5f, 0xd7f, 0xd9f, 0xdbf, 0xddf, 0xdff, 0xe1f, 0xe3f, 0xe5f, 0xe7f, 0xe9f, 0xebf, 0xedf, 0xeff, 0xf1f, 0xf3f, 0xf5f, 0xf7f, 0xf9f, 0xfbf, 0xfdf,
0xfff, 0xfdf, 0xfbf, 0xf9f, 0xf7f, 0xf5f, 0xf3f, 0xf1f, 0xeff, 0xedf, 0xebf, 0xe9f, 0xe7f, 0xe5f, 0xe3f, 0xe1f, 0xdff, 0xddf, 0xdbf, 0xd9f, 0xd7f, 0xd5f, 0xd3f, 0xd1f, 0xcff, 0xcdf, 0xcbf, 0xc9f, 0xc7f, 0xc5f, 0xc3f, 0xc1f, 0xbff, 0xbdf, 0xbbf, 0xb9f, 0xb7f, 0xb5f, 0xb3f, 0xb1f, 0xaff, 0xadf, 0xabf, 0xa9f, 0xa7f, 0xa5f, 0xa3f, 0xa1f, 0x9ff, 0x9df, 0x9bf, 0x99f, 0x97f, 0x95f, 0x93f, 0x91f, 0x8ff, 0x8df, 0x8bf, 0x89f, 0x87f, 0x85f, 0x83f, 0x81f, 0x800, 0x7e0, 0x7c0, 0x7a0, 0x780, 0x760, 0x740, 0x720, 0x700, 0x6e0, 0x6c0, 0x6a0, 0x680, 0x660, 0x640, 0x620, 0x600, 0x5e0, 0x5c0, 0x5a0, 0x580, 0x560, 0x540, 0x520, 0x500, 0x4e0, 0x4c0, 0x4a0, 0x480, 0x460, 0x440, 0x420, 0x400, 0x3e0, 0x3c0, 0x3a0, 0x380, 0x360, 0x340, 0x320, 0x300, 0x2e0, 0x2c0, 0x2a0, 0x280, 0x260, 0x240, 0x220, 0x200, 0x1e0, 0x1c0, 0x1a0, 0x180, 0x160, 0x140, 0x120, 0x100, 0xe0, 0xc0, 0xa0, 0x80, 0x60, 0x40, 0x20};
#endif // AUDIO_DAC_SAMPLE_WAVEFORM_TRIANGLE
#ifdef AUDIO_DAC_SAMPLE_WAVEFORM_SQUARE
static const dacsample_t dac_buffer_square[AUDIO_DAC_BUFFER_SIZE] = {
[0 ... AUDIO_DAC_BUFFER_SIZE / 2 - 1] = 0, // first and
[AUDIO_DAC_BUFFER_SIZE / 2 ... AUDIO_DAC_BUFFER_SIZE - 1] = AUDIO_DAC_SAMPLE_MAX, // second half
};
#endif // AUDIO_DAC_SAMPLE_WAVEFORM_SQUARE
/*
// four steps: 0, 1/3, 2/3 and 1
static const dacsample_t dac_buffer_staircase[AUDIO_DAC_BUFFER_SIZE] = {
[0 ... AUDIO_DAC_BUFFER_SIZE/3 -1 ] = 0,
[AUDIO_DAC_BUFFER_SIZE / 4 ... AUDIO_DAC_BUFFER_SIZE / 2 -1 ] = AUDIO_DAC_SAMPLE_MAX / 3,
[AUDIO_DAC_BUFFER_SIZE / 2 ... 3 * AUDIO_DAC_BUFFER_SIZE / 4 -1 ] = 2 * AUDIO_DAC_SAMPLE_MAX / 3,
[3 * AUDIO_DAC_BUFFER_SIZE / 4 ... AUDIO_DAC_BUFFER_SIZE -1 ] = AUDIO_DAC_SAMPLE_MAX,
}
*/
#ifdef AUDIO_DAC_SAMPLE_WAVEFORM_TRAPEZOID
static const dacsample_t dac_buffer_trapezoid[AUDIO_DAC_BUFFER_SIZE] = {0x0, 0x1f, 0x7f, 0xdf, 0x13f, 0x19f, 0x1ff, 0x25f, 0x2bf, 0x31f, 0x37f, 0x3df, 0x43f, 0x49f, 0x4ff, 0x55f, 0x5bf, 0x61f, 0x67f, 0x6df, 0x73f, 0x79f, 0x7ff, 0x85f, 0x8bf, 0x91f, 0x97f, 0x9df, 0xa3f, 0xa9f, 0xaff, 0xb5f, 0xbbf, 0xc1f, 0xc7f, 0xcdf, 0xd3f, 0xd9f, 0xdff, 0xe5f, 0xebf, 0xf1f, 0xf7f, 0xfdf, 0xfff, 0xfff, 0xfff, 0xfff, 0xfff, 0xfff, 0xfff, 0xfff, 0xfff, 0xfff, 0xfff, 0xfff, 0xfff, 0xfff, 0xfff, 0xfff, 0xfff, 0xfff, 0xfff, 0xfff, 0xfff, 0xfff, 0xfff, 0xfff, 0xfff, 0xfff, 0xfff, 0xfff, 0xfff, 0xfff, 0xfff, 0xfff, 0xfff, 0xfff, 0xfff, 0xfff, 0xfff, 0xfff, 0xfff, 0xfff, 0xfff, 0xfff, 0xfff, 0xfff, 0xfff, 0xfff, 0xfff, 0xfff, 0xfff, 0xfff, 0xfff, 0xfff, 0xfff, 0xfff, 0xfff, 0xfff, 0xfff, 0xfff, 0xfff, 0xfff, 0xfff, 0xfff, 0xfff, 0xfff, 0xfff, 0xfff, 0xfff, 0xfff, 0xfff, 0xfff, 0xfff, 0xfff, 0xfff, 0xfff, 0xfff, 0xfff, 0xfff, 0xfff, 0xfff, 0xfff, 0xfff, 0xfff, 0xfff, 0xfff,
0xfff, 0xfdf, 0xf7f, 0xf1f, 0xebf, 0xe5f, 0xdff, 0xd9f, 0xd3f, 0xcdf, 0xc7f, 0xc1f, 0xbbf, 0xb5f, 0xaff, 0xa9f, 0xa3f, 0x9df, 0x97f, 0x91f, 0x8bf, 0x85f, 0x7ff, 0x79f, 0x73f, 0x6df, 0x67f, 0x61f, 0x5bf, 0x55f, 0x4ff, 0x49f, 0x43f, 0x3df, 0x37f, 0x31f, 0x2bf, 0x25f, 0x1ff, 0x19f, 0x13f, 0xdf, 0x7f, 0x1f, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0};
#endif // AUDIO_DAC_SAMPLE_WAVEFORM_TRAPEZOID
static dacsample_t dac_buffer_empty[AUDIO_DAC_BUFFER_SIZE] = {AUDIO_DAC_OFF_VALUE};
/* keep track of the sample position for for each frequency */
static float dac_if[AUDIO_MAX_SIMULTANEOUS_TONES] = {0.0};
static float active_tones_snapshot[AUDIO_MAX_SIMULTANEOUS_TONES] = {0, 0};
static uint8_t active_tones_snapshot_length = 0;
typedef enum {
OUTPUT_SHOULD_START,
OUTPUT_RUN_NORMALLY,
// path 1: wait for zero, then change/update active tones
OUTPUT_TONES_CHANGED,
OUTPUT_REACHED_ZERO_BEFORE_TONE_CHANGE,
// path 2: hardware should stop, wait for zero then turn output off = stop the timer
OUTPUT_SHOULD_STOP,
OUTPUT_REACHED_ZERO_BEFORE_OFF,
OUTPUT_OFF,
OUTPUT_OFF_1,
OUTPUT_OFF_2, // trailing off: giving the DAC two more conversion cycles until the AUDIO_DAC_OFF_VALUE reaches the output, then turn the timer off, which leaves the output at that level
number_of_output_states
} output_states_t;
output_states_t state = OUTPUT_OFF_2;
/**
* Generation of the waveform being passed to the callback. Declared weak so users
* can override it with their own wave-forms/noises.
*/
__attribute__((weak)) uint16_t dac_value_generate(void) {
// DAC is running/asking for values but snapshot length is zero -> must be playing a pause
if (active_tones_snapshot_length == 0) {
return AUDIO_DAC_OFF_VALUE;
}
/* doing additive wave synthesis over all currently playing tones = adding up
* sine-wave-samples for each frequency, scaled by the number of active tones
*/
uint16_t value = 0;
float frequency = 0.0f;
for (uint8_t i = 0; i < active_tones_snapshot_length; i++) {
/* Note: a user implementation does not have to rely on the active_tones_snapshot, but
* could directly query the active frequencies through audio_get_processed_frequency */
frequency = active_tones_snapshot[i];
dac_if[i] = dac_if[i] + ((frequency * AUDIO_DAC_BUFFER_SIZE) / AUDIO_DAC_SAMPLE_RATE) * 2 / 3;
/*Note: the 2/3 are necessary to get the correct frequencies on the
* DAC output (as measured with an oscilloscope), since the gpt
* timer runs with 3*AUDIO_DAC_SAMPLE_RATE; and the DAC callback
* is called twice per conversion.*/
dac_if[i] = fmod(dac_if[i], AUDIO_DAC_BUFFER_SIZE);
// Wavetable generation/lookup
uint16_t dac_i = (uint16_t)dac_if[i];
#if defined(AUDIO_DAC_SAMPLE_WAVEFORM_SINE)
value += dac_buffer_sine[dac_i] / active_tones_snapshot_length;
#elif defined(AUDIO_DAC_SAMPLE_WAVEFORM_TRIANGLE)
value += dac_buffer_triangle[dac_i] / active_tones_snapshot_length;
#elif defined(AUDIO_DAC_SAMPLE_WAVEFORM_TRAPEZOID)
value += dac_buffer_trapezoid[dac_i] / active_tones_snapshot_length;
#elif defined(AUDIO_DAC_SAMPLE_WAVEFORM_SQUARE)
value += dac_buffer_square[dac_i] / active_tones_snapshot_length;
#endif
/*
// SINE
value += dac_buffer_sine[dac_i] / active_tones_snapshot_length / 3;
// TRIANGLE
value += dac_buffer_triangle[dac_i] / active_tones_snapshot_length / 3;
// SQUARE
value += dac_buffer_square[dac_i] / active_tones_snapshot_length / 3;
//NOTE: combination of these three wave-forms is more exemplary - and doesn't sound particularly good :-P
*/
// STAIRS (mostly usefully as test-pattern)
// value_avg = dac_buffer_staircase[dac_i] / active_tones_snapshot_length;
}
return value;
}
/**
* DAC streaming callback. Does all of the main computing for playing songs.
*
* Note: chibios calls this CB twice: during the 'half buffer event', and the 'full buffer event'.
*/
static void dac_end(DACDriver *dacp) {
dacsample_t *sample_p = (dacp)->samples;
// work on the other half of the buffer
if (dacIsBufferComplete(dacp)) {
sample_p += AUDIO_DAC_BUFFER_SIZE / 2; // 'half_index'
}
for (uint8_t s = 0; s < AUDIO_DAC_BUFFER_SIZE / 2; s++) {
if (OUTPUT_OFF <= state) {
sample_p[s] = AUDIO_DAC_OFF_VALUE;
continue;
} else {
sample_p[s] = dac_value_generate();
}
/* zero crossing (or approach, whereas zero == DAC_OFF_VALUE, which can be configured to anything from 0 to DAC_SAMPLE_MAX)
* ============================*=*========================== AUDIO_DAC_SAMPLE_MAX
* * *
* * *
* ---------------------------------------------------------
* * * } AUDIO_DAC_SAMPLE_MAX/100
* --------------------------------------------------------- AUDIO_DAC_OFF_VALUE
* * * } AUDIO_DAC_SAMPLE_MAX/100
* ---------------------------------------------------------
* *
* * *
* * *
* =====*=*================================================= 0x0
*/
if (((sample_p[s] + (AUDIO_DAC_SAMPLE_MAX / 100)) > AUDIO_DAC_OFF_VALUE) && // value approaches from below
(sample_p[s] < (AUDIO_DAC_OFF_VALUE + (AUDIO_DAC_SAMPLE_MAX / 100))) // or above
) {
if ((OUTPUT_SHOULD_START == state) && (active_tones_snapshot_length > 0)) {
state = OUTPUT_RUN_NORMALLY;
} else if (OUTPUT_TONES_CHANGED == state) {
state = OUTPUT_REACHED_ZERO_BEFORE_TONE_CHANGE;
} else if (OUTPUT_SHOULD_STOP == state) {
state = OUTPUT_REACHED_ZERO_BEFORE_OFF;
}
}
// still 'ramping up', reset the output to OFF_VALUE until the generated values reach that value, to do a smooth handover
if (OUTPUT_SHOULD_START == state) {
sample_p[s] = AUDIO_DAC_OFF_VALUE;
}
if ((OUTPUT_SHOULD_START == state) || (OUTPUT_REACHED_ZERO_BEFORE_OFF == state) || (OUTPUT_REACHED_ZERO_BEFORE_TONE_CHANGE == state)) {
uint8_t active_tones = MIN(AUDIO_MAX_SIMULTANEOUS_TONES, audio_get_number_of_active_tones());
active_tones_snapshot_length = 0;
// update the snapshot - once, and only on occasion that something changed;
// -> saves cpu cycles (?)
for (uint8_t i = 0; i < active_tones; i++) {
float freq = audio_get_processed_frequency(i);
if (freq > 0) { // disregard 'rest' notes, with valid frequency 0.0f; which would only lower the resulting waveform volume during the additive synthesis step
active_tones_snapshot[active_tones_snapshot_length++] = freq;
}
}
if ((0 == active_tones_snapshot_length) && (OUTPUT_REACHED_ZERO_BEFORE_OFF == state)) {
state = OUTPUT_OFF;
}
if (OUTPUT_REACHED_ZERO_BEFORE_TONE_CHANGE == state) {
state = OUTPUT_RUN_NORMALLY;
}
}
}
// update audio internal state (note position, current_note, ...)
if (audio_update_state()) {
if (OUTPUT_SHOULD_STOP != state) {
state = OUTPUT_TONES_CHANGED;
}
}
if (OUTPUT_OFF <= state) {
if (OUTPUT_OFF_2 == state) {
// stopping timer6 = stopping the DAC at whatever value it is currently pushing to the output = AUDIO_DAC_OFF_VALUE
gptStopTimer(&GPTD6);
} else {
state++;
}
}
}
static void dac_error(DACDriver *dacp, dacerror_t err) {
(void)dacp;
(void)err;
chSysHalt("DAC failure. halp");
}
static const GPTConfig gpt6cfg1 = {.frequency = AUDIO_DAC_SAMPLE_RATE * 3,
.callback = NULL,
.cr2 = TIM_CR2_MMS_1, /* MMS = 010 = TRGO on Update Event. */
.dier = 0U};
static const DACConfig dac_conf = {.init = AUDIO_DAC_OFF_VALUE, .datamode = DAC_DHRM_12BIT_RIGHT};
/**
* @note The DAC_TRG(0) here selects the Timer 6 TRGO event, which is triggered
* on the rising edge after 3 APB1 clock cycles, causing our gpt6cfg1.frequency
* to be a third of what we expect.
*
* Here are all the values for DAC_TRG (TSEL in the ref manual)
* TIM15_TRGO 0b011
* TIM2_TRGO 0b100
* TIM3_TRGO 0b001
* TIM6_TRGO 0b000
* TIM7_TRGO 0b010
* EXTI9 0b110
* SWTRIG 0b111
*/
static const DACConversionGroup dac_conv_cfg = {.num_channels = 1U, .end_cb = dac_end, .error_cb = dac_error, .trigger = DAC_TRG(0b000)};
void audio_driver_initialize() {
if ((AUDIO_PIN == A4) || (AUDIO_PIN_ALT == A4)) {
palSetLineMode(A4, PAL_MODE_INPUT_ANALOG);
dacStart(&DACD1, &dac_conf);
}
if ((AUDIO_PIN == A5) || (AUDIO_PIN_ALT == A5)) {
palSetLineMode(A5, PAL_MODE_INPUT_ANALOG);
dacStart(&DACD2, &dac_conf);
}
/* enable the output buffer, to directly drive external loads with no additional circuitry
*
* see: AN4566 Application note: Extending the DAC performance of STM32 microcontrollers
* Note: Buffer-Off bit -> has to be set 0 to enable the output buffer
* Note: enabling the output buffer imparts an additional dc-offset of a couple mV
*
* this is done here, reaching directly into the stm32 registers since chibios has not implemented BOFF handling yet
* (see: chibios/os/hal/ports/STM32/todo.txt '- BOFF handling in DACv1.'
*/
DACD1.params->dac->CR &= ~DAC_CR_BOFF1;
DACD2.params->dac->CR &= ~DAC_CR_BOFF2;
if (AUDIO_PIN == A4) {
dacStartConversion(&DACD1, &dac_conv_cfg, dac_buffer_empty, AUDIO_DAC_BUFFER_SIZE);
} else if (AUDIO_PIN == A5) {
dacStartConversion(&DACD2, &dac_conv_cfg, dac_buffer_empty, AUDIO_DAC_BUFFER_SIZE);
}
// no inverted/out-of-phase waveform (yet?), only pulling AUDIO_PIN_ALT to AUDIO_DAC_OFF_VALUE
#if defined(AUDIO_PIN_ALT_AS_NEGATIVE)
if (AUDIO_PIN_ALT == A4) {
dacPutChannelX(&DACD1, 0, AUDIO_DAC_OFF_VALUE);
} else if (AUDIO_PIN_ALT == A5) {
dacPutChannelX(&DACD2, 0, AUDIO_DAC_OFF_VALUE);
}
#endif
gptStart(&GPTD6, &gpt6cfg1);
}
void audio_driver_stop(void) { state = OUTPUT_SHOULD_STOP; }
void audio_driver_start(void) {
gptStartContinuous(&GPTD6, 2U);
for (uint8_t i = 0; i < AUDIO_MAX_SIMULTANEOUS_TONES; i++) {
dac_if[i] = 0.0f;
active_tones_snapshot[i] = 0.0f;
}
active_tones_snapshot_length = 0;
state = OUTPUT_SHOULD_START;
}

245
platforms/chibios/drivers/audio_dac_basic.c Normal file
View File

@@ -0,0 +1,245 @@
/* Copyright 2016-2020 Jack Humbert
* Copyright 2020 JohSchneider
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#include "audio.h"
#include "ch.h"
#include "hal.h"
/*
Audio Driver: DAC
which utilizes both channels of the DAC unit many STM32 are equipped with to output a modulated square-wave, from precomputed samples stored in a buffer, which is passed to the hardware through DMA
this driver can either be used to drive to separate speakers, wired to A4+Gnd and A5+Gnd, which allows two tones to be played simultaneously
OR
one speaker wired to A4+A5 with the AUDIO_PIN_ALT_AS_NEGATIVE define set - see docs/feature_audio
*/
#if !defined(AUDIO_PIN)
# pragma message "Audio feature enabled, but no suitable pin selected as AUDIO_PIN - see docs/feature_audio under 'ARM (DAC basic)' for available options."
// TODO: make this an 'error' instead; go through a breaking change, and add AUDIO_PIN A5 to all keyboards currently using AUDIO on STM32 based boards? - for now: set the define here
# define AUDIO_PIN A5
#endif
// check configuration for ONE speaker, connected to both DAC pins
#if defined(AUDIO_PIN_ALT_AS_NEGATIVE) && !defined(AUDIO_PIN_ALT)
# error "Audio feature: AUDIO_PIN_ALT_AS_NEGATIVE set, but no pin configured as AUDIO_PIN_ALT"
#endif
#ifndef AUDIO_PIN_ALT
// no ALT pin defined is valid, but the c-ifs below need some value set
# define AUDIO_PIN_ALT -1
#endif
#if !defined(AUDIO_STATE_TIMER)
# define AUDIO_STATE_TIMER GPTD8
#endif
// square-wave
static const dacsample_t dac_buffer_1[AUDIO_DAC_BUFFER_SIZE] = {
// First half is max, second half is 0
[0 ... AUDIO_DAC_BUFFER_SIZE / 2 - 1] = AUDIO_DAC_SAMPLE_MAX,
[AUDIO_DAC_BUFFER_SIZE / 2 ... AUDIO_DAC_BUFFER_SIZE - 1] = 0,
};
// square-wave
static const dacsample_t dac_buffer_2[AUDIO_DAC_BUFFER_SIZE] = {
// opposite of dac_buffer above
[0 ... AUDIO_DAC_BUFFER_SIZE / 2 - 1] = 0,
[AUDIO_DAC_BUFFER_SIZE / 2 ... AUDIO_DAC_BUFFER_SIZE - 1] = AUDIO_DAC_SAMPLE_MAX,
};
GPTConfig gpt6cfg1 = {.frequency = AUDIO_DAC_SAMPLE_RATE,
.callback = NULL,
.cr2 = TIM_CR2_MMS_1, /* MMS = 010 = TRGO on Update Event. */
.dier = 0U};
GPTConfig gpt7cfg1 = {.frequency = AUDIO_DAC_SAMPLE_RATE,
.callback = NULL,
.cr2 = TIM_CR2_MMS_1, /* MMS = 010 = TRGO on Update Event. */
.dier = 0U};
static void gpt_audio_state_cb(GPTDriver *gptp);
GPTConfig gptStateUpdateCfg = {.frequency = 10,
.callback = gpt_audio_state_cb,
.cr2 = TIM_CR2_MMS_1, /* MMS = 010 = TRGO on Update Event. */
.dier = 0U};
static const DACConfig dac_conf_ch1 = {.init = AUDIO_DAC_OFF_VALUE, .datamode = DAC_DHRM_12BIT_RIGHT};
static const DACConfig dac_conf_ch2 = {.init = AUDIO_DAC_OFF_VALUE, .datamode = DAC_DHRM_12BIT_RIGHT};
/**
* @note The DAC_TRG(0) here selects the Timer 6 TRGO event, which is triggered
* on the rising edge after 3 APB1 clock cycles, causing our gpt6cfg1.frequency
* to be a third of what we expect.
*
* Here are all the values for DAC_TRG (TSEL in the ref manual)
* TIM15_TRGO 0b011
* TIM2_TRGO 0b100
* TIM3_TRGO 0b001
* TIM6_TRGO 0b000
* TIM7_TRGO 0b010
* EXTI9 0b110
* SWTRIG 0b111
*/
static const DACConversionGroup dac_conv_grp_ch1 = {.num_channels = 1U, .trigger = DAC_TRG(0b000)};
static const DACConversionGroup dac_conv_grp_ch2 = {.num_channels = 1U, .trigger = DAC_TRG(0b010)};
void channel_1_start(void) {
gptStart(&GPTD6, &gpt6cfg1);
gptStartContinuous(&GPTD6, 2U);
palSetPadMode(GPIOA, 4, PAL_MODE_INPUT_ANALOG);
}
void channel_1_stop(void) {
gptStopTimer(&GPTD6);
palSetPadMode(GPIOA, 4, PAL_MODE_OUTPUT_PUSHPULL);
palSetPad(GPIOA, 4);
}
static float channel_1_frequency = 0.0f;
void channel_1_set_frequency(float freq) {
channel_1_frequency = freq;
channel_1_stop();
if (freq <= 0.0) // a pause/rest has freq=0
return;
gpt6cfg1.frequency = 2 * freq * AUDIO_DAC_BUFFER_SIZE;
channel_1_start();
}
float channel_1_get_frequency(void) { return channel_1_frequency; }
void channel_2_start(void) {
gptStart(&GPTD7, &gpt7cfg1);
gptStartContinuous(&GPTD7, 2U);
palSetPadMode(GPIOA, 5, PAL_MODE_INPUT_ANALOG);
}
void channel_2_stop(void) {
gptStopTimer(&GPTD7);
palSetPadMode(GPIOA, 5, PAL_MODE_OUTPUT_PUSHPULL);
palSetPad(GPIOA, 5);
}
static float channel_2_frequency = 0.0f;
void channel_2_set_frequency(float freq) {
channel_2_frequency = freq;
channel_2_stop();
if (freq <= 0.0) // a pause/rest has freq=0
return;
gpt7cfg1.frequency = 2 * freq * AUDIO_DAC_BUFFER_SIZE;
channel_2_start();
}
float channel_2_get_frequency(void) { return channel_2_frequency; }
static void gpt_audio_state_cb(GPTDriver *gptp) {
if (audio_update_state()) {
#if defined(AUDIO_PIN_ALT_AS_NEGATIVE)
// one piezo/speaker connected to both audio pins, the generated square-waves are inverted
channel_1_set_frequency(audio_get_processed_frequency(0));
channel_2_set_frequency(audio_get_processed_frequency(0));
#else // two separate audio outputs/speakers
// primary speaker on A4, optional secondary on A5
if (AUDIO_PIN == A4) {
channel_1_set_frequency(audio_get_processed_frequency(0));
if (AUDIO_PIN_ALT == A5) {
if (audio_get_number_of_active_tones() > 1) {
channel_2_set_frequency(audio_get_processed_frequency(1));
} else {
channel_2_stop();
}
}
}
// primary speaker on A5, optional secondary on A4
if (AUDIO_PIN == A5) {
channel_2_set_frequency(audio_get_processed_frequency(0));
if (AUDIO_PIN_ALT == A4) {
if (audio_get_number_of_active_tones() > 1) {
channel_1_set_frequency(audio_get_processed_frequency(1));
} else {
channel_1_stop();
}
}
}
#endif
}
}
void audio_driver_initialize() {
if ((AUDIO_PIN == A4) || (AUDIO_PIN_ALT == A4)) {
palSetPadMode(GPIOA, 4, PAL_MODE_INPUT_ANALOG);
dacStart(&DACD1, &dac_conf_ch1);
// initial setup of the dac-triggering timer is still required, even
// though it gets reconfigured and restarted later on
gptStart(&GPTD6, &gpt6cfg1);
}
if ((AUDIO_PIN == A5) || (AUDIO_PIN_ALT == A5)) {
palSetPadMode(GPIOA, 5, PAL_MODE_INPUT_ANALOG);
dacStart(&DACD2, &dac_conf_ch2);
gptStart(&GPTD7, &gpt7cfg1);
}
/* enable the output buffer, to directly drive external loads with no additional circuitry
*
* see: AN4566 Application note: Extending the DAC performance of STM32 microcontrollers
* Note: Buffer-Off bit -> has to be set 0 to enable the output buffer
* Note: enabling the output buffer imparts an additional dc-offset of a couple mV
*
* this is done here, reaching directly into the stm32 registers since chibios has not implemented BOFF handling yet
* (see: chibios/os/hal/ports/STM32/todo.txt '- BOFF handling in DACv1.'
*/
DACD1.params->dac->CR &= ~DAC_CR_BOFF1;
DACD2.params->dac->CR &= ~DAC_CR_BOFF2;
// start state-updater
gptStart(&AUDIO_STATE_TIMER, &gptStateUpdateCfg);
}
void audio_driver_stop(void) {
if ((AUDIO_PIN == A4) || (AUDIO_PIN_ALT == A4)) {
gptStopTimer(&GPTD6);
// stop the ongoing conversion and put the output in a known state
dacStopConversion(&DACD1);
dacPutChannelX(&DACD1, 0, AUDIO_DAC_OFF_VALUE);
}
if ((AUDIO_PIN == A5) || (AUDIO_PIN_ALT == A5)) {
gptStopTimer(&GPTD7);
dacStopConversion(&DACD2);
dacPutChannelX(&DACD2, 0, AUDIO_DAC_OFF_VALUE);
}
gptStopTimer(&AUDIO_STATE_TIMER);
}
void audio_driver_start(void) {
if ((AUDIO_PIN == A4) || (AUDIO_PIN_ALT == A4)) {
dacStartConversion(&DACD1, &dac_conv_grp_ch1, (dacsample_t *)dac_buffer_1, AUDIO_DAC_BUFFER_SIZE);
}
if ((AUDIO_PIN == A5) || (AUDIO_PIN_ALT == A5)) {
dacStartConversion(&DACD2, &dac_conv_grp_ch2, (dacsample_t *)dac_buffer_2, AUDIO_DAC_BUFFER_SIZE);
}
gptStartContinuous(&AUDIO_STATE_TIMER, 2U);
}

40
platforms/chibios/drivers/audio_pwm.h Normal file
View File

@@ -0,0 +1,40 @@
/* Copyright 2020 Jack Humbert
* Copyright 2020 JohSchneider
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#pragma once
#if !defined(AUDIO_PWM_DRIVER)
// NOTE: Timer2 seems to be used otherwise in QMK, otherwise we could default to A5 (= TIM2_CH1, with PWMD2 and alternate-function(1))
# define AUDIO_PWM_DRIVER PWMD1
#endif
#if !defined(AUDIO_PWM_CHANNEL)
// NOTE: sticking to the STM data-sheet numbering: TIMxCH1 to TIMxCH4
// default: STM32F303CC PA8+TIM1_CH1 -> 1
# define AUDIO_PWM_CHANNEL 1
#endif
#if !defined(AUDIO_PWM_PAL_MODE)
// pin-alternate function: see the data-sheet for which pin needs what AF to connect to TIMx_CHy
// default: STM32F303CC PA8+TIM1_CH1 -> 6
# define AUDIO_PWM_PAL_MODE 6
#endif
#if !defined(AUDIO_STATE_TIMER)
// timer used to trigger updates in the audio-system, configured/enabled in chibios mcuconf.
// Tim6 is the default for "larger" STMs, smaller ones might not have this one (enabled) and need to switch to a different one (e.g.: STM32F103 has only Tim1-Tim4)
# define AUDIO_STATE_TIMER GPTD6
#endif

144
platforms/chibios/drivers/audio_pwm_hardware.c Normal file
View File

@@ -0,0 +1,144 @@
/* Copyright 2020 Jack Humbert
* Copyright 2020 JohSchneider
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
/*
Audio Driver: PWM
the duty-cycle is always kept at 50%, and the pwm-period is adjusted to match the frequency of a note to be played back.
this driver uses the chibios-PWM system to produce a square-wave on specific output pins that are connected to the PWM hardware.
The hardware directly toggles the pin via its alternate function. see your MCUs data-sheet for which pin can be driven by what timer - looking for TIMx_CHy and the corresponding alternate function.
*/
#include "audio.h"
#include "ch.h"
#include "hal.h"
#if !defined(AUDIO_PIN)
# error "Audio feature enabled, but no pin selected - see docs/feature_audio under the ARM PWM settings"
#endif
extern bool playing_note;
extern bool playing_melody;
extern uint8_t note_timbre;
static PWMConfig pwmCFG = {
.frequency = 100000, /* PWM clock frequency */
// CHIBIOS-BUG? can't set the initial period to <2, or the pwm (hard or software) takes ~130ms with .frequency=500000 for a pwmChangePeriod to take effect; with no output=silence in the meantime
.period = 2, /* initial PWM period (in ticks) 1S (1/10kHz=0.1mS 0.1ms*10000 ticks=1S) */
.callback = NULL, /* no callback, the hardware directly toggles the pin */
.channels =
{
#if AUDIO_PWM_CHANNEL == 4
{PWM_OUTPUT_DISABLED, NULL}, /* channel 0 -> TIMx_CH1 */
{PWM_OUTPUT_DISABLED, NULL}, /* channel 1 -> TIMx_CH2 */
{PWM_OUTPUT_DISABLED, NULL}, /* channel 2 -> TIMx_CH3 */
{PWM_OUTPUT_ACTIVE_HIGH, NULL} /* channel 3 -> TIMx_CH4 */
#elif AUDIO_PWM_CHANNEL == 3
{PWM_OUTPUT_DISABLED, NULL},
{PWM_OUTPUT_DISABLED, NULL},
{PWM_OUTPUT_ACTIVE_HIGH, NULL}, /* TIMx_CH3 */
{PWM_OUTPUT_DISABLED, NULL}
#elif AUDIO_PWM_CHANNEL == 2
{PWM_OUTPUT_DISABLED, NULL},
{PWM_OUTPUT_ACTIVE_HIGH, NULL}, /* TIMx_CH2 */
{PWM_OUTPUT_DISABLED, NULL},
{PWM_OUTPUT_DISABLED, NULL}
#else /*fallback to CH1 */
{PWM_OUTPUT_ACTIVE_HIGH, NULL}, /* TIMx_CH1 */
{PWM_OUTPUT_DISABLED, NULL},
{PWM_OUTPUT_DISABLED, NULL},
{PWM_OUTPUT_DISABLED, NULL}
#endif
},
};
static float channel_1_frequency = 0.0f;
void channel_1_set_frequency(float freq) {
channel_1_frequency = freq;
if (freq <= 0.0) // a pause/rest has freq=0
return;
pwmcnt_t period = (pwmCFG.frequency / freq);
pwmChangePeriod(&AUDIO_PWM_DRIVER, period);
pwmEnableChannel(&AUDIO_PWM_DRIVER, AUDIO_PWM_CHANNEL - 1,
// adjust the duty-cycle so that the output is for 'note_timbre' duration HIGH
PWM_PERCENTAGE_TO_WIDTH(&AUDIO_PWM_DRIVER, (100 - note_timbre) * 100));
}
float channel_1_get_frequency(void) { return channel_1_frequency; }
void channel_1_start(void) {
pwmStop(&AUDIO_PWM_DRIVER);
pwmStart(&AUDIO_PWM_DRIVER, &pwmCFG);
}
void channel_1_stop(void) { pwmStop(&AUDIO_PWM_DRIVER); }
static void gpt_callback(GPTDriver *gptp);
GPTConfig gptCFG = {
/* a whole note is one beat, which is - per definition in musical_notes.h - set to 64
the longest note is BREAVE_DOT=128+64=192, the shortest SIXTEENTH=4
the tempo (which might vary!) is in bpm (beats per minute)
therefore: if the timer ticks away at .frequency = (60*64)Hz,
and the .interval counts from 64 downwards - audio_update_state is
called just often enough to not miss any notes
*/
.frequency = 60 * 64,
.callback = gpt_callback,
};
void audio_driver_initialize(void) {
pwmStart(&AUDIO_PWM_DRIVER, &pwmCFG);
// connect the AUDIO_PIN to the PWM hardware
#if defined(USE_GPIOV1) // STM32F103C8
palSetLineMode(AUDIO_PIN, PAL_MODE_ALTERNATE_PUSHPULL);
#else // GPIOv2 (or GPIOv3 for f4xx, which is the same/compatible at this command)
palSetLineMode(AUDIO_PIN, PAL_MODE_ALTERNATE(AUDIO_PWM_PAL_MODE));
#endif
gptStart(&AUDIO_STATE_TIMER, &gptCFG);
}
void audio_driver_start(void) {
channel_1_stop();
channel_1_start();
if (playing_note || playing_melody) {
gptStartContinuous(&AUDIO_STATE_TIMER, 64);
}
}
void audio_driver_stop(void) {
channel_1_stop();
gptStopTimer(&AUDIO_STATE_TIMER);
}
/* a regular timer task, that checks the note to be currently played
* and updates the pwm to output that frequency
*/
static void gpt_callback(GPTDriver *gptp) {
float freq; // TODO: freq_alt
if (audio_update_state()) {
freq = audio_get_processed_frequency(0); // freq_alt would be index=1
channel_1_set_frequency(freq);
}
}

164
platforms/chibios/drivers/audio_pwm_software.c Normal file
View File

@@ -0,0 +1,164 @@
/* Copyright 2020 Jack Humbert
* Copyright 2020 JohSchneider
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
/*
Audio Driver: PWM
the duty-cycle is always kept at 50%, and the pwm-period is adjusted to match the frequency of a note to be played back.
this driver uses the chibios-PWM system to produce a square-wave on any given output pin in software
- a pwm callback is used to set/clear the configured pin.
*/
#include "audio.h"
#include "ch.h"
#include "hal.h"
#if !defined(AUDIO_PIN)
# error "Audio feature enabled, but no pin selected - see docs/feature_audio under the ARM PWM settings"
#endif
extern bool playing_note;
extern bool playing_melody;
extern uint8_t note_timbre;
static void pwm_audio_period_callback(PWMDriver *pwmp);
static void pwm_audio_channel_interrupt_callback(PWMDriver *pwmp);
static PWMConfig pwmCFG = {
.frequency = 100000, /* PWM clock frequency */
// CHIBIOS-BUG? can't set the initial period to <2, or the pwm (hard or software) takes ~130ms with .frequency=500000 for a pwmChangePeriod to take effect; with no output=silence in the meantime
.period = 2, /* initial PWM period (in ticks) 1S (1/10kHz=0.1mS 0.1ms*10000 ticks=1S) */
.callback = pwm_audio_period_callback,
.channels =
{
// software-PWM just needs another callback on any channel
{PWM_OUTPUT_ACTIVE_HIGH, pwm_audio_channel_interrupt_callback}, /* channel 0 -> TIMx_CH1 */
{PWM_OUTPUT_DISABLED, NULL}, /* channel 1 -> TIMx_CH2 */
{PWM_OUTPUT_DISABLED, NULL}, /* channel 2 -> TIMx_CH3 */
{PWM_OUTPUT_DISABLED, NULL} /* channel 3 -> TIMx_CH4 */
},
};
static float channel_1_frequency = 0.0f;
void channel_1_set_frequency(float freq) {
channel_1_frequency = freq;
if (freq <= 0.0) // a pause/rest has freq=0
return;
pwmcnt_t period = (pwmCFG.frequency / freq);
pwmChangePeriod(&AUDIO_PWM_DRIVER, period);
pwmEnableChannel(&AUDIO_PWM_DRIVER, AUDIO_PWM_CHANNEL - 1,
// adjust the duty-cycle so that the output is for 'note_timbre' duration HIGH
PWM_PERCENTAGE_TO_WIDTH(&AUDIO_PWM_DRIVER, (100 - note_timbre) * 100));
}
float channel_1_get_frequency(void) { return channel_1_frequency; }
void channel_1_start(void) {
pwmStop(&AUDIO_PWM_DRIVER);
pwmStart(&AUDIO_PWM_DRIVER, &pwmCFG);
pwmEnablePeriodicNotification(&AUDIO_PWM_DRIVER);
pwmEnableChannelNotification(&AUDIO_PWM_DRIVER, AUDIO_PWM_CHANNEL - 1);
}
void channel_1_stop(void) {
pwmStop(&AUDIO_PWM_DRIVER);
palClearLine(AUDIO_PIN); // leave the line low, after last note was played
#if defined(AUDIO_PIN_ALT) && defined(AUDIO_PIN_ALT_AS_NEGATIVE)
palClearLine(AUDIO_PIN_ALT); // leave the line low, after last note was played
#endif
}
// generate a PWM signal on any pin, not necessarily the one connected to the timer
static void pwm_audio_period_callback(PWMDriver *pwmp) {
(void)pwmp;
palClearLine(AUDIO_PIN);
#if defined(AUDIO_PIN_ALT) && defined(AUDIO_PIN_ALT_AS_NEGATIVE)
palSetLine(AUDIO_PIN_ALT);
#endif
}
static void pwm_audio_channel_interrupt_callback(PWMDriver *pwmp) {
(void)pwmp;
if (channel_1_frequency > 0) {
palSetLine(AUDIO_PIN); // generate a PWM signal on any pin, not necessarily the one connected to the timer
#if defined(AUDIO_PIN_ALT) && defined(AUDIO_PIN_ALT_AS_NEGATIVE)
palClearLine(AUDIO_PIN_ALT);
#endif
}
}
static void gpt_callback(GPTDriver *gptp);
GPTConfig gptCFG = {
/* a whole note is one beat, which is - per definition in musical_notes.h - set to 64
the longest note is BREAVE_DOT=128+64=192, the shortest SIXTEENTH=4
the tempo (which might vary!) is in bpm (beats per minute)
therefore: if the timer ticks away at .frequency = (60*64)Hz,
and the .interval counts from 64 downwards - audio_update_state is
called just often enough to not miss anything
*/
.frequency = 60 * 64,
.callback = gpt_callback,
};
void audio_driver_initialize(void) {
pwmStart(&AUDIO_PWM_DRIVER, &pwmCFG);
palSetLineMode(AUDIO_PIN, PAL_MODE_OUTPUT_PUSHPULL);
palClearLine(AUDIO_PIN);
#if defined(AUDIO_PIN_ALT) && defined(AUDIO_PIN_ALT_AS_NEGATIVE)
palSetLineMode(AUDIO_PIN_ALT, PAL_MODE_OUTPUT_PUSHPULL);
palClearLine(AUDIO_PIN_ALT);
#endif
pwmEnablePeriodicNotification(&AUDIO_PWM_DRIVER); // enable pwm callbacks
pwmEnableChannelNotification(&AUDIO_PWM_DRIVER, AUDIO_PWM_CHANNEL - 1);
gptStart(&AUDIO_STATE_TIMER, &gptCFG);
}
void audio_driver_start(void) {
channel_1_stop();
channel_1_start();
if (playing_note || playing_melody) {
gptStartContinuous(&AUDIO_STATE_TIMER, 64);
}
}
void audio_driver_stop(void) {
channel_1_stop();
gptStopTimer(&AUDIO_STATE_TIMER);
}
/* a regular timer task, that checks the note to be currently played
* and updates the pwm to output that frequency
*/
static void gpt_callback(GPTDriver *gptp) {
float freq; // TODO: freq_alt
if (audio_update_state()) {
freq = audio_get_processed_frequency(0); // freq_alt would be index=1
channel_1_set_frequency(freq);
}
}

40
platforms/chibios/drivers/i2c_master.c
View File

@@ -38,6 +38,9 @@ static const I2CConfig i2cconfig = {
I2C1_OPMODE,
I2C1_CLOCK_SPEED,
I2C1_DUTY_CYCLE,
#elif defined(WB32F3G71xx)
I2C1_OPMODE,
I2C1_CLOCK_SPEED,
#else
// This configures the I2C clock to 400khz assuming a 72Mhz clock
// For more info : https://www.st.com/en/embedded-software/stsw-stm32126.html
@@ -63,16 +66,16 @@ __attribute__((weak)) void i2c_init(void) {
is_initialised = true;
// Try releasing special pins for a short time
palSetPadMode(I2C1_SCL_BANK, I2C1_SCL, PAL_MODE_INPUT);
palSetPadMode(I2C1_SDA_BANK, I2C1_SDA, PAL_MODE_INPUT);
palSetLineMode(I2C1_SCL_PIN, PAL_MODE_INPUT);
palSetLineMode(I2C1_SDA_PIN, PAL_MODE_INPUT);
chThdSleepMilliseconds(10);
#if defined(USE_GPIOV1)
palSetPadMode(I2C1_SCL_BANK, I2C1_SCL, I2C1_SCL_PAL_MODE);
palSetPadMode(I2C1_SDA_BANK, I2C1_SDA, I2C1_SDA_PAL_MODE);
palSetLineMode(I2C1_SCL_PIN, I2C1_SCL_PAL_MODE);
palSetLineMode(I2C1_SDA_PIN, I2C1_SDA_PAL_MODE);
#else
palSetPadMode(I2C1_SCL_BANK, I2C1_SCL, PAL_MODE_ALTERNATE(I2C1_SCL_PAL_MODE) | PAL_STM32_OTYPE_OPENDRAIN);
palSetPadMode(I2C1_SDA_BANK, I2C1_SDA, PAL_MODE_ALTERNATE(I2C1_SDA_PAL_MODE) | PAL_STM32_OTYPE_OPENDRAIN);
palSetLineMode(I2C1_SCL_PIN, PAL_MODE_ALTERNATE(I2C1_SCL_PAL_MODE) | PAL_OUTPUT_TYPE_OPENDRAIN);
palSetLineMode(I2C1_SDA_PIN, PAL_MODE_ALTERNATE(I2C1_SDA_PAL_MODE) | PAL_OUTPUT_TYPE_OPENDRAIN);
#endif
}
}
@@ -102,7 +105,7 @@ i2c_status_t i2c_writeReg(uint8_t devaddr, uint8_t regaddr, const uint8_t* data,
i2cStart(&I2C_DRIVER, &i2cconfig);
uint8_t complete_packet[length + 1];
for (uint8_t i = 0; i < length; i++) {
for (uint16_t i = 0; i < length; i++) {
complete_packet[i + 1] = data[i];
}
complete_packet[0] = regaddr;
@@ -111,6 +114,21 @@ i2c_status_t i2c_writeReg(uint8_t devaddr, uint8_t regaddr, const uint8_t* data,
return chibios_to_qmk(&status);
}
i2c_status_t i2c_writeReg16(uint8_t devaddr, uint16_t regaddr, const uint8_t* data, uint16_t length, uint16_t timeout) {
i2c_address = devaddr;
i2cStart(&I2C_DRIVER, &i2cconfig);
uint8_t complete_packet[length + 2];
for (uint16_t i = 0; i < length; i++) {
complete_packet[i + 2] = data[i];
}
complete_packet[0] = regaddr >> 8;
complete_packet[1] = regaddr & 0xFF;
msg_t status = i2cMasterTransmitTimeout(&I2C_DRIVER, (i2c_address >> 1), complete_packet, length + 2, 0, 0, TIME_MS2I(timeout));
return chibios_to_qmk(&status);
}
i2c_status_t i2c_readReg(uint8_t devaddr, uint8_t regaddr, uint8_t* data, uint16_t length, uint16_t timeout) {
i2c_address = devaddr;
i2cStart(&I2C_DRIVER, &i2cconfig);
@@ -118,4 +136,12 @@ i2c_status_t i2c_readReg(uint8_t devaddr, uint8_t regaddr, uint8_t* data, uint16
return chibios_to_qmk(&status);
}
i2c_status_t i2c_readReg16(uint8_t devaddr, uint16_t regaddr, uint8_t* data, uint16_t length, uint16_t timeout) {
i2c_address = devaddr;
i2cStart(&I2C_DRIVER, &i2cconfig);
uint8_t register_packet[2] = {regaddr >> 8, regaddr & 0xFF};
msg_t status = i2cMasterTransmitTimeout(&I2C_DRIVER, (i2c_address >> 1), register_packet, 2, data, length, TIME_MS2I(timeout));
return chibios_to_qmk(&status);
}
void i2c_stop(void) { i2cStop(&I2C_DRIVER); }

27
platforms/chibios/drivers/i2c_master.h
View File

@@ -27,24 +27,11 @@
#include <ch.h>
#include <hal.h>
#ifdef I2C1_BANK
# define I2C1_SCL_BANK I2C1_BANK
# define I2C1_SDA_BANK I2C1_BANK
#ifndef I2C1_SCL_PIN
# define I2C1_SCL_PIN B6
#endif
#ifndef I2C1_SCL_BANK
# define I2C1_SCL_BANK GPIOB
#endif
#ifndef I2C1_SDA_BANK
# define I2C1_SDA_BANK GPIOB
#endif
#ifndef I2C1_SCL
# define I2C1_SCL 6
#endif
#ifndef I2C1_SDA
# define I2C1_SDA 7
#ifndef I2C1_SDA_PIN
# define I2C1_SDA_PIN B7
#endif
#ifdef USE_I2CV1
@@ -83,10 +70,10 @@
#ifdef USE_GPIOV1
# ifndef I2C1_SCL_PAL_MODE
# define I2C1_SCL_PAL_MODE PAL_MODE_STM32_ALTERNATE_OPENDRAIN
# define I2C1_SCL_PAL_MODE PAL_MODE_ALTERNATE_OPENDRAIN
# endif
# ifndef I2C1_SDA_PAL_MODE
# define I2C1_SDA_PAL_MODE PAL_MODE_STM32_ALTERNATE_OPENDRAIN
# define I2C1_SDA_PAL_MODE PAL_MODE_ALTERNATE_OPENDRAIN
# endif
#else
// The default PAL alternate modes are used to signal that the pins are used for I2C
@@ -109,5 +96,7 @@ i2c_status_t i2c_start(uint8_t address);
i2c_status_t i2c_transmit(uint8_t address, const uint8_t* data, uint16_t length, uint16_t timeout);
i2c_status_t i2c_receive(uint8_t address, uint8_t* data, uint16_t length, uint16_t timeout);
i2c_status_t i2c_writeReg(uint8_t devaddr, uint8_t regaddr, const uint8_t* data, uint16_t length, uint16_t timeout);
i2c_status_t i2c_writeReg16(uint8_t devaddr, uint16_t regaddr, const uint8_t* data, uint16_t length, uint16_t timeout);
i2c_status_t i2c_readReg(uint8_t devaddr, uint8_t regaddr, uint8_t* data, uint16_t length, uint16_t timeout);
i2c_status_t i2c_readReg16(uint8_t devaddr, uint16_t regaddr, uint8_t* data, uint16_t length, uint16_t timeout);
void i2c_stop(void);

55
platforms/chibios/drivers/ps2/ps2_io.c Normal file
View File

@@ -0,0 +1,55 @@
#include <stdbool.h>
#include "ps2_io.h"
// chibiOS headers
#include "ch.h"
#include "hal.h"
/* Check port settings for clock and data line */
#if !(defined(PS2_CLOCK_PIN))
# error "PS/2 clock setting is required in config.h"
#endif
#if !(defined(PS2_DATA_PIN))
# error "PS/2 data setting is required in config.h"
#endif
/*
* Clock
*/
void clock_init(void) {}
void clock_lo(void) {
palSetLineMode(PS2_CLOCK_PIN, PAL_MODE_OUTPUT_OPENDRAIN);
palWriteLine(PS2_CLOCK_PIN, PAL_LOW);
}
void clock_hi(void) {
palSetLineMode(PS2_CLOCK_PIN, PAL_MODE_OUTPUT_OPENDRAIN);
palWriteLine(PS2_CLOCK_PIN, PAL_HIGH);
}
bool clock_in(void) {
palSetLineMode(PS2_CLOCK_PIN, PAL_MODE_INPUT);
return palReadLine(PS2_CLOCK_PIN);
}
/*
* Data
*/
void data_init(void) {}
void data_lo(void) {
palSetLineMode(PS2_DATA_PIN, PAL_MODE_OUTPUT_OPENDRAIN);
palWriteLine(PS2_DATA_PIN, PAL_LOW);
}
void data_hi(void) {
palSetLineMode(PS2_DATA_PIN, PAL_MODE_OUTPUT_OPENDRAIN);
palWriteLine(PS2_DATA_PIN, PAL_HIGH);
}
bool data_in(void) {
palSetLineMode(PS2_DATA_PIN, PAL_MODE_INPUT);
return palReadLine(PS2_DATA_PIN);
}

2
platforms/chibios/drivers/serial.c
View File

@@ -19,7 +19,7 @@
# error "chSysPolledDelayX method not supported on this platform"
#else
# undef wait_us
# define wait_us(x) chSysPolledDelayX(US2RTC(STM32_SYSCLK, x))
# define wait_us(x) chSysPolledDelayX(US2RTC(CPU_CLOCK, x))
#endif
#ifndef SELECT_SOFT_SERIAL_SPEED

10
platforms/chibios/drivers/serial_usart.c
View File

@@ -104,9 +104,9 @@ static inline bool receive(uint8_t* destination, const size_t size) {
__attribute__((weak)) void usart_init(void) {
# if defined(MCU_STM32)
# if defined(USE_GPIOV1)
palSetLineMode(SERIAL_USART_TX_PIN, PAL_MODE_STM32_ALTERNATE_OPENDRAIN);
palSetLineMode(SERIAL_USART_TX_PIN, PAL_MODE_ALTERNATE_OPENDRAIN);
# else
palSetLineMode(SERIAL_USART_TX_PIN, PAL_MODE_ALTERNATE(SERIAL_USART_TX_PAL_MODE) | PAL_STM32_OTYPE_OPENDRAIN);
palSetLineMode(SERIAL_USART_TX_PIN, PAL_MODE_ALTERNATE(SERIAL_USART_TX_PAL_MODE) | PAL_OUTPUT_TYPE_OPENDRAIN);
# endif
# if defined(USART_REMAP)
@@ -125,11 +125,11 @@ __attribute__((weak)) void usart_init(void) {
__attribute__((weak)) void usart_init(void) {
# if defined(MCU_STM32)
# if defined(USE_GPIOV1)
palSetLineMode(SERIAL_USART_TX_PIN, PAL_MODE_STM32_ALTERNATE_PUSHPULL);
palSetLineMode(SERIAL_USART_TX_PIN, PAL_MODE_ALTERNATE_PUSHPULL);
palSetLineMode(SERIAL_USART_RX_PIN, PAL_MODE_INPUT);
# else
palSetLineMode(SERIAL_USART_TX_PIN, PAL_MODE_ALTERNATE(SERIAL_USART_TX_PAL_MODE) | PAL_STM32_OTYPE_PUSHPULL | PAL_STM32_OSPEED_HIGHEST);
palSetLineMode(SERIAL_USART_RX_PIN, PAL_MODE_ALTERNATE(SERIAL_USART_RX_PAL_MODE) | PAL_STM32_OTYPE_PUSHPULL | PAL_STM32_OSPEED_HIGHEST);
palSetLineMode(SERIAL_USART_TX_PIN, PAL_MODE_ALTERNATE(SERIAL_USART_TX_PAL_MODE) | PAL_OUTPUT_TYPE_PUSHPULL | PAL_OUTPUT_SPEED_HIGHEST);
palSetLineMode(SERIAL_USART_RX_PIN, PAL_MODE_ALTERNATE(SERIAL_USART_RX_PAL_MODE) | PAL_OUTPUT_TYPE_PUSHPULL | PAL_OUTPUT_SPEED_HIGHEST);
# endif
# if defined(USART_REMAP)

64
platforms/chibios/drivers/spi_master.c
View File

@@ -42,9 +42,9 @@ __attribute__((weak)) void spi_init(void) {
palSetPadMode(PAL_PORT(SPI_MOSI_PIN), PAL_PAD(SPI_MOSI_PIN), SPI_MOSI_PAL_MODE);
palSetPadMode(PAL_PORT(SPI_MISO_PIN), PAL_PAD(SPI_MISO_PIN), SPI_MISO_PAL_MODE);
#else
palSetPadMode(PAL_PORT(SPI_SCK_PIN), PAL_PAD(SPI_SCK_PIN), PAL_MODE_ALTERNATE(SPI_SCK_PAL_MODE) | PAL_STM32_OTYPE_PUSHPULL | PAL_STM32_OSPEED_HIGHEST);
palSetPadMode(PAL_PORT(SPI_MOSI_PIN), PAL_PAD(SPI_MOSI_PIN), PAL_MODE_ALTERNATE(SPI_MOSI_PAL_MODE) | PAL_STM32_OTYPE_PUSHPULL | PAL_STM32_OSPEED_HIGHEST);
palSetPadMode(PAL_PORT(SPI_MISO_PIN), PAL_PAD(SPI_MISO_PIN), PAL_MODE_ALTERNATE(SPI_MISO_PAL_MODE) | PAL_STM32_OTYPE_PUSHPULL | PAL_STM32_OSPEED_HIGHEST);
palSetPadMode(PAL_PORT(SPI_SCK_PIN), PAL_PAD(SPI_SCK_PIN), PAL_MODE_ALTERNATE(SPI_SCK_PAL_MODE) | PAL_OUTPUT_TYPE_PUSHPULL | PAL_OUTPUT_SPEED_HIGHEST);
palSetPadMode(PAL_PORT(SPI_MOSI_PIN), PAL_PAD(SPI_MOSI_PIN), PAL_MODE_ALTERNATE(SPI_MOSI_PAL_MODE) | PAL_OUTPUT_TYPE_PUSHPULL | PAL_OUTPUT_SPEED_HIGHEST);
palSetPadMode(PAL_PORT(SPI_MISO_PIN), PAL_PAD(SPI_MISO_PIN), PAL_MODE_ALTERNATE(SPI_MISO_PAL_MODE) | PAL_OUTPUT_TYPE_PUSHPULL | PAL_OUTPUT_SPEED_HIGHEST);
#endif
}
}
@@ -54,6 +54,7 @@ bool spi_start(pin_t slavePin, bool lsbFirst, uint8_t mode, uint16_t divisor) {
return false;
}
#ifndef WB32F3G71xx
uint16_t roundedDivisor = 2;
while (roundedDivisor < divisor) {
roundedDivisor <<= 1;
@@ -62,6 +63,7 @@ bool spi_start(pin_t slavePin, bool lsbFirst, uint8_t mode, uint16_t divisor) {
if (roundedDivisor < 2 || roundedDivisor > 256) {
return false;
}
#endif
#if defined(K20x) || defined(KL2x)
spiConfig.tar0 = SPIx_CTARn_FMSZ(7) | SPIx_CTARn_ASC(1);
@@ -110,6 +112,62 @@ bool spi_start(pin_t slavePin, bool lsbFirst, uint8_t mode, uint16_t divisor) {
spiConfig.tar0 |= SPIx_CTARn_BR(8);
break;
}
#elif defined(HT32)
spiConfig.cr0 = SPI_CR0_SELOEN;
spiConfig.cr1 = SPI_CR1_MODE | 8; // 8 bits and in master mode
if (lsbFirst) {
spiConfig.cr1 |= SPI_CR1_FIRSTBIT;
}
switch (mode) {
case 0:
spiConfig.cr1 |= SPI_CR1_FORMAT_MODE0;
break;
case 1:
spiConfig.cr1 |= SPI_CR1_FORMAT_MODE1;
break;
case 2:
spiConfig.cr1 |= SPI_CR1_FORMAT_MODE2;
break;
case 3:
spiConfig.cr1 |= SPI_CR1_FORMAT_MODE3;
break;
}
spiConfig.cpr = (roundedDivisor - 1) >> 1;
#elif defined(WB32F3G71xx)
if (!lsbFirst) {
osalDbgAssert(lsbFirst != FALSE, "unsupported lsbFirst");
}
if (divisor < 1) {
return false;
}
spiConfig.SPI_BaudRatePrescaler = (divisor << 2);
switch (mode) {
case 0:
spiConfig.SPI_CPHA = SPI_CPHA_1Edge;
spiConfig.SPI_CPOL = SPI_CPOL_Low;
break;
case 1:
spiConfig.SPI_CPHA = SPI_CPHA_2Edge;
spiConfig.SPI_CPOL = SPI_CPOL_Low;
break;
case 2:
spiConfig.SPI_CPHA = SPI_CPHA_1Edge;
spiConfig.SPI_CPOL = SPI_CPOL_High;
break;
case 3:
spiConfig.SPI_CPHA = SPI_CPHA_2Edge;
spiConfig.SPI_CPOL = SPI_CPOL_High;
break;
}
#else
spiConfig.cr1 = 0;

6
platforms/chibios/drivers/spi_master.h
View File

@@ -33,7 +33,7 @@
#ifndef SPI_SCK_PAL_MODE
# if defined(USE_GPIOV1)
# define SPI_SCK_PAL_MODE PAL_MODE_STM32_ALTERNATE_PUSHPULL
# define SPI_SCK_PAL_MODE PAL_MODE_ALTERNATE_PUSHPULL
# else
# define SPI_SCK_PAL_MODE 5
# endif
@@ -45,7 +45,7 @@
#ifndef SPI_MOSI_PAL_MODE
# if defined(USE_GPIOV1)
# define SPI_MOSI_PAL_MODE PAL_MODE_STM32_ALTERNATE_PUSHPULL
# define SPI_MOSI_PAL_MODE PAL_MODE_ALTERNATE_PUSHPULL
# else
# define SPI_MOSI_PAL_MODE 5
# endif
@@ -57,7 +57,7 @@
#ifndef SPI_MISO_PAL_MODE
# if defined(USE_GPIOV1)
# define SPI_MISO_PAL_MODE PAL_MODE_STM32_ALTERNATE_PUSHPULL
# define SPI_MISO_PAL_MODE PAL_MODE_ALTERNATE_PUSHPULL
# else
# define SPI_MISO_PAL_MODE 5
# endif

20
platforms/chibios/drivers/uart.c
View File

@@ -18,7 +18,11 @@
#include "quantum.h"
#if defined(WB32F3G71xx)
static SerialConfig serialConfig = {SERIAL_DEFAULT_BITRATE, SD1_WRDLEN, SD1_STPBIT, SD1_PARITY, SD1_ATFLCT};
#else
static SerialConfig serialConfig = {SERIAL_DEFAULT_BITRATE, SD1_CR1, SD1_CR2, SD1_CR3};
#endif
void uart_init(uint32_t baud) {
static bool is_initialised = false;
@@ -29,22 +33,26 @@ void uart_init(uint32_t baud) {
serialConfig.speed = baud;
#if defined(USE_GPIOV1)
palSetLineMode(SD1_TX_PIN, PAL_MODE_STM32_ALTERNATE_OPENDRAIN);
palSetLineMode(SD1_RX_PIN, PAL_MODE_STM32_ALTERNATE_OPENDRAIN);
palSetLineMode(SD1_TX_PIN, PAL_MODE_ALTERNATE_OPENDRAIN);
palSetLineMode(SD1_RX_PIN, PAL_MODE_ALTERNATE_OPENDRAIN);
#else
palSetLineMode(SD1_TX_PIN, PAL_MODE_ALTERNATE(SD1_TX_PAL_MODE) | PAL_STM32_OTYPE_OPENDRAIN);
palSetLineMode(SD1_RX_PIN, PAL_MODE_ALTERNATE(SD1_RX_PAL_MODE) | PAL_STM32_OTYPE_OPENDRAIN);
palSetLineMode(SD1_TX_PIN, PAL_MODE_ALTERNATE(SD1_TX_PAL_MODE) | PAL_OUTPUT_TYPE_OPENDRAIN);
palSetLineMode(SD1_RX_PIN, PAL_MODE_ALTERNATE(SD1_RX_PAL_MODE) | PAL_OUTPUT_TYPE_OPENDRAIN);
#endif
sdStart(&SERIAL_DRIVER, &serialConfig);
}
}
void uart_putchar(uint8_t c) { sdPut(&SERIAL_DRIVER, c); }
void uart_write(uint8_t data) { sdPut(&SERIAL_DRIVER, c); }
uint8_t uart_getchar(void) {
uint8_t uart_read(void) {
msg_t res = sdGet(&SERIAL_DRIVER);
return (uint8_t)res;
}
void uart_transmit(const uint8_t *data, uint16_t length) { sdWrite(&SERIAL_DRIVER, data, length); }
void uart_receive(uint8_t *data, uint16_t length) { sdRead(&SERIAL_DRIVER, data, length); }
bool uart_available(void) { return !sdGetWouldBlock(&SERIAL_DRIVER); }

24
platforms/chibios/drivers/uart.h
View File

@@ -68,10 +68,30 @@
# define SD1_CR3 0
#endif
#ifndef SD1_WRDLEN
# define SD1_WRDLEN 3
#endif
#ifndef SD1_STPBIT
# define SD1_STPBIT 0
#endif
#ifndef SD1_PARITY
# define SD1_PARITY 0
#endif
#ifndef SD1_ATFLCT
# define SD1_ATFLCT 0
#endif
void uart_init(uint32_t baud);
void uart_putchar(uint8_t c);
void uart_write(uint8_t data);
uint8_t uart_getchar(void);
uint8_t uart_read(void);
void uart_transmit(const uint8_t *data, uint16_t length);
void uart_receive(uint8_t *data, uint16_t length);
bool uart_available(void);

33
platforms/chibios/drivers/ws2812.c
View File

@@ -6,7 +6,7 @@
/* Adapted from https://github.com/bigjosh/SimpleNeoPixelDemo/ */
#ifndef NOP_FUDGE
# if defined(STM32F0XX) || defined(STM32F1XX) || defined(STM32F3XX) || defined(STM32F4XX) || defined(STM32L0XX)
# if defined(STM32F0XX) || defined(STM32F1XX) || defined(GD32VF103) || defined(STM32F3XX) || defined(STM32F4XX) || defined(STM32L0XX)
# define NOP_FUDGE 0.4
# else
# error("NOP_FUDGE configuration required")
@@ -22,8 +22,14 @@
# define WS2812_OUTPUT_MODE PAL_MODE_OUTPUT_OPENDRAIN
#endif
// The reset gap can be 6000 ns, but depending on the LED strip it may have to be increased
// to values like 600000 ns. If it is too small, the pixels will show nothing most of the time.
#ifndef WS2812_RES
# define WS2812_RES (1000 * WS2812_TRST_US) // Width of the low gap between bits to cause a frame to latch
#endif
#define NUMBER_NOPS 6
#define CYCLES_PER_SEC (STM32_SYSCLK / NUMBER_NOPS * NOP_FUDGE)
#define CYCLES_PER_SEC (CPU_CLOCK / NUMBER_NOPS * NOP_FUDGE)
#define NS_PER_SEC (1000000000L) // Note that this has to be SIGNED since we want to be able to check for negative values of derivatives
#define NS_PER_CYCLE (NS_PER_SEC / CYCLES_PER_SEC)
#define NS_TO_CYCLES(n) ((n) / NS_PER_CYCLE)
@@ -40,19 +46,6 @@
} \
} while (0)
// These are the timing constraints taken mostly from the WS2812 datasheets
// These are chosen to be conservative and avoid problems rather than for maximum throughput
#define T1H 900 // Width of a 1 bit in ns
#define T1L (1250 - T1H) // Width of a 1 bit in ns
#define T0H 350 // Width of a 0 bit in ns
#define T0L (1250 - T0H) // Width of a 0 bit in ns
// The reset gap can be 6000 ns, but depending on the LED strip it may have to be increased
// to values like 600000 ns. If it is too small, the pixels will show nothing most of the time.
#define RES (1000 * WS2812_TRST_US) // Width of the low gap between bits to cause a frame to latch
void sendByte(uint8_t byte) {
// WS2812 protocol wants most significant bits first
for (unsigned char bit = 0; bit < 8; bit++) {
@@ -61,15 +54,15 @@ void sendByte(uint8_t byte) {
if (is_one) {
// 1
writePinHigh(RGB_DI_PIN);
wait_ns(T1H);
wait_ns(WS2812_T1H);
writePinLow(RGB_DI_PIN);
wait_ns(T1L);
wait_ns(WS2812_T1L);
} else {
// 0
writePinHigh(RGB_DI_PIN);
wait_ns(T0H);
wait_ns(WS2812_T0H);
writePinLow(RGB_DI_PIN);
wait_ns(T0L);
wait_ns(WS2812_T0L);
}
}
}
@@ -108,7 +101,7 @@ void ws2812_setleds(LED_TYPE *ledarray, uint16_t leds) {
#endif
}
wait_ns(RES);
wait_ns(WS2812_RES);
chSysUnlock();
}

50
platforms/chibios/drivers/ws2812_pwm.c
View File

@@ -5,7 +5,9 @@
/* Adapted from https://github.com/joewa/WS2812-LED-Driver_ChibiOS/ */
#ifdef RGBW
# error "RGBW not supported"
# define WS2812_CHANNELS 4
#else
# define WS2812_CHANNELS 3
#endif
#ifndef WS2812_PWM_DRIVER
@@ -40,15 +42,15 @@
// Default Push Pull
#ifndef WS2812_EXTERNAL_PULLUP
# if defined(USE_GPIOV1)
# define WS2812_OUTPUT_MODE PAL_MODE_STM32_ALTERNATE_PUSHPULL
# define WS2812_OUTPUT_MODE PAL_MODE_ALTERNATE_PUSHPULL
# else
# define WS2812_OUTPUT_MODE PAL_MODE_ALTERNATE(WS2812_PWM_PAL_MODE) | PAL_STM32_OTYPE_PUSHPULL | PAL_STM32_OSPEED_HIGHEST | PAL_STM32_PUPDR_FLOATING
# define WS2812_OUTPUT_MODE PAL_MODE_ALTERNATE(WS2812_PWM_PAL_MODE) | PAL_OUTPUT_TYPE_PUSHPULL | PAL_OUTPUT_SPEED_HIGHEST | PAL_PUPDR_FLOATING
# endif
#else
# if defined(USE_GPIOV1)
# define WS2812_OUTPUT_MODE PAL_MODE_STM32_ALTERNATE_OPENDRAIN
# define WS2812_OUTPUT_MODE PAL_MODE_ALTERNATE_OPENDRAIN
# else
# define WS2812_OUTPUT_MODE PAL_MODE_ALTERNATE(WS2812_PWM_PAL_MODE) | PAL_STM32_OTYPE_OPENDRAIN | PAL_STM32_OSPEED_HIGHEST | PAL_STM32_PUPDR_FLOATING
# define WS2812_OUTPUT_MODE PAL_MODE_ALTERNATE(WS2812_PWM_PAL_MODE) | PAL_OUTPUT_TYPE_OPENDRAIN | PAL_OUTPUT_SPEED_HIGHEST | PAL_PUPDR_FLOATING
# endif
#endif
@@ -59,7 +61,7 @@
/* --- PRIVATE CONSTANTS ---------------------------------------------------- */
#define WS2812_PWM_FREQUENCY (STM32_SYSCLK / 2) /**< Clock frequency of PWM, must be valid with respect to system clock! */
#define WS2812_PWM_FREQUENCY (CPU_CLOCK / 2) /**< Clock frequency of PWM, must be valid with respect to system clock! */
#define WS2812_PWM_PERIOD (WS2812_PWM_FREQUENCY / WS2812_PWM_TARGET_PERIOD) /**< Clock period in ticks. 1 / 800kHz = 1.25 uS (as per datasheet) */
/**
@@ -68,8 +70,9 @@
* The reset period for each frame is defined in WS2812_TRST_US.
* Calculate the number of zeroes to add at the end assuming 1.25 uS/bit:
*/
#define WS2812_RESET_BIT_N (1000 * WS2812_TRST_US / 1250)
#define WS2812_COLOR_BIT_N (RGBLED_NUM * 24) /**< Number of data bits */
#define WS2812_COLOR_BITS (WS2812_CHANNELS * 8)
#define WS2812_RESET_BIT_N (1000 * WS2812_TRST_US / WS2812_TIMING)
#define WS2812_COLOR_BIT_N (RGBLED_NUM * WS2812_COLOR_BITS) /**< Number of data bits */
#define WS2812_BIT_N (WS2812_COLOR_BIT_N + WS2812_RESET_BIT_N) /**< Total number of bits in a frame */
/**
@@ -114,7 +117,7 @@
*
* @return The bit index
*/
#define WS2812_BIT(led, byte, bit) (24 * (led) + 8 * (byte) + (7 - (bit)))
#define WS2812_BIT(led, byte, bit) (WS2812_COLOR_BITS * (led) + 8 * (byte) + (7 - (bit)))
#if (WS2812_BYTE_ORDER == WS2812_BYTE_ORDER_GRB)
/**
@@ -228,6 +231,20 @@
# define WS2812_BLUE_BIT(led, bit) WS2812_BIT((led), 0, (bit))
#endif
#ifdef RGBW
/**
* @brief Determine the index in @ref ws2812_frame_buffer "the frame buffer" of a given white bit
*
* @note The white byte is the last byte in the color packet
*
* @param[in] led: The led index [0, @ref WS2812_LED_N)
* @param[in] bit: The bit index [0, 7]
*
* @return The bit index
*/
# define WS2812_WHITE_BIT(led, bit) WS2812_BIT((led), 3, (bit))
#endif
/* --- PRIVATE VARIABLES ---------------------------------------------------- */
static uint32_t ws2812_frame_buffer[WS2812_BIT_N + 1]; /**< Buffer for a frame */
@@ -296,6 +313,17 @@ void ws2812_write_led(uint16_t led_number, uint8_t r, uint8_t g, uint8_t b) {
ws2812_frame_buffer[WS2812_BLUE_BIT(led_number, bit)] = ((b >> bit) & 0x01) ? WS2812_DUTYCYCLE_1 : WS2812_DUTYCYCLE_0;
}
}
void ws2812_write_led_rgbw(uint16_t led_number, uint8_t r, uint8_t g, uint8_t b, uint8_t w) {
// Write color to frame buffer
for (uint8_t bit = 0; bit < 8; bit++) {
ws2812_frame_buffer[WS2812_RED_BIT(led_number, bit)] = ((r >> bit) & 0x01) ? WS2812_DUTYCYCLE_1 : WS2812_DUTYCYCLE_0;
ws2812_frame_buffer[WS2812_GREEN_BIT(led_number, bit)] = ((g >> bit) & 0x01) ? WS2812_DUTYCYCLE_1 : WS2812_DUTYCYCLE_0;
ws2812_frame_buffer[WS2812_BLUE_BIT(led_number, bit)] = ((b >> bit) & 0x01) ? WS2812_DUTYCYCLE_1 : WS2812_DUTYCYCLE_0;
#ifdef RGBW
ws2812_frame_buffer[WS2812_WHITE_BIT(led_number, bit)] = ((w >> bit) & 0x01) ? WS2812_DUTYCYCLE_1 : WS2812_DUTYCYCLE_0;
#endif
}
}
// Setleds for standard RGB
void ws2812_setleds(LED_TYPE* ledarray, uint16_t leds) {
@@ -306,6 +334,10 @@ void ws2812_setleds(LED_TYPE* ledarray, uint16_t leds) {
}
for (uint16_t i = 0; i < leds; i++) {
#ifdef RGBW
ws2812_write_led_rgbw(i, ledarray[i].r, ledarray[i].g, ledarray[i].b, ledarray[i].w);
#else
ws2812_write_led(i, ledarray[i].r, ledarray[i].g, ledarray[i].b);
#endif
}
}

29
platforms/chibios/drivers/ws2812_spi.c
View File

@@ -3,10 +3,6 @@
/* Adapted from https://github.com/gamazeps/ws2812b-chibios-SPIDMA/ */
#ifdef RGBW
# error "RGBW not supported"
#endif
// Define the spi your LEDs are plugged to here
#ifndef WS2812_SPI
# define WS2812_SPI SPID1
@@ -24,15 +20,15 @@
// Default Push Pull
#ifndef WS2812_EXTERNAL_PULLUP
# if defined(USE_GPIOV1)
# define WS2812_MOSI_OUTPUT_MODE PAL_MODE_STM32_ALTERNATE_PUSHPULL
# define WS2812_MOSI_OUTPUT_MODE PAL_MODE_ALTERNATE_PUSHPULL
# else
# define WS2812_MOSI_OUTPUT_MODE PAL_MODE_ALTERNATE(WS2812_SPI_MOSI_PAL_MODE) | PAL_STM32_OTYPE_PUSHPULL
# define WS2812_MOSI_OUTPUT_MODE PAL_MODE_ALTERNATE(WS2812_SPI_MOSI_PAL_MODE) | PAL_OUTPUT_TYPE_PUSHPULL
# endif
#else
# if defined(USE_GPIOV1)
# define WS2812_MOSI_OUTPUT_MODE PAL_MODE_STM32_ALTERNATE_OPENDRAIN
# define WS2812_MOSI_OUTPUT_MODE PAL_MODE_ALTERNATE_OPENDRAIN
# else
# define WS2812_MOSI_OUTPUT_MODE PAL_MODE_ALTERNATE(WS2812_SPI_MOSI_PAL_MODE) | PAL_STM32_OTYPE_OPENDRAIN
# define WS2812_MOSI_OUTPUT_MODE PAL_MODE_ALTERNATE(WS2812_SPI_MOSI_PAL_MODE) | PAL_OUTPUT_TYPE_OPENDRAIN
# endif
#endif
@@ -68,16 +64,20 @@
#endif
#if defined(USE_GPIOV1)
# define WS2812_SCK_OUTPUT_MODE PAL_MODE_STM32_ALTERNATE_PUSHPULL
# define WS2812_SCK_OUTPUT_MODE PAL_MODE_ALTERNATE_PUSHPULL
#else
# define WS2812_SCK_OUTPUT_MODE PAL_MODE_ALTERNATE(WS2812_SPI_SCK_PAL_MODE) | PAL_STM32_OTYPE_PUSHPULL
# define WS2812_SCK_OUTPUT_MODE PAL_MODE_ALTERNATE(WS2812_SPI_SCK_PAL_MODE) | PAL_OUTPUT_TYPE_PUSHPULL
#endif
#define BYTES_FOR_LED_BYTE 4
#define NB_COLORS 3
#define BYTES_FOR_LED (BYTES_FOR_LED_BYTE * NB_COLORS)
#ifdef RGBW
# define WS2812_CHANNELS 4
#else
# define WS2812_CHANNELS 3
#endif
#define BYTES_FOR_LED (BYTES_FOR_LED_BYTE * WS2812_CHANNELS)
#define DATA_SIZE (BYTES_FOR_LED * RGBLED_NUM)
#define RESET_SIZE (1000 * WS2812_TRST_US / (2 * 1250))
#define RESET_SIZE (1000 * WS2812_TRST_US / (2 * WS2812_TIMING))
#define PREAMBLE_SIZE 4
static uint8_t txbuf[PREAMBLE_SIZE + DATA_SIZE + RESET_SIZE] = {0};
@@ -116,6 +116,9 @@ static void set_led_color_rgb(LED_TYPE color, int pos) {
for (int j = 0; j < 4; j++) tx_start[BYTES_FOR_LED * pos + BYTES_FOR_LED_BYTE + j] = get_protocol_eq(color.g, j);
for (int j = 0; j < 4; j++) tx_start[BYTES_FOR_LED * pos + BYTES_FOR_LED_BYTE * 2 + j] = get_protocol_eq(color.r, j);
#endif
#ifdef RGBW
for (int j = 0; j < 4; j++) tx_start[BYTES_FOR_LED * pos + BYTES_FOR_LED_BYTE * 4 + j] = get_protocol_eq(color.w, j);
#endif
}
void ws2812_init(void) {

18
platforms/chibios/drivers/wt_rgb_backlight.c
View File

@@ -68,7 +68,7 @@ LED_TYPE g_ws2812_leds[WS2812_LED_TOTAL];
#include "progmem.h"
#include "quantum/color.h"
#include "tmk_core/common/eeprom.h"
#include "eeprom.h"
#include "via.h" // uses EEPROM address, lighting value IDs
#define RGB_BACKLIGHT_CONFIG_EEPROM_ADDR (VIA_EEPROM_CUSTOM_CONFIG_ADDR)
@@ -158,7 +158,7 @@ uint32_t g_any_key_hit = 0;
// ADDR_2 is not needed. it is here as a dummy
#define ISSI_ADDR_1 0x50
const is31_led __flash g_is31_leds[DRIVER_LED_TOTAL] = {
const is31_led PROGMEM g_is31_leds[DRIVER_LED_TOTAL] = {
/* Refer to IS31 manual for these locations
* driver
* | R location
@@ -239,7 +239,7 @@ const is31_led __flash g_is31_leds[DRIVER_LED_TOTAL] = {
#define ISSI_ADDR_1 0x50
#define ISSI_ADDR_2 0x52
const is31_led __flash g_is31_leds[DRIVER_LED_TOTAL] = {
const is31_led PROGMEM g_is31_leds[DRIVER_LED_TOTAL] = {
/* Refer to IS31 manual for these locations
* driver
* | R location
@@ -382,7 +382,7 @@ const is31_led __flash g_is31_leds[DRIVER_LED_TOTAL] = {
// set to 0 for write, 1 for read (as per I2C protocol)
#define ISSI_ADDR_1 0x74
const is31_led __flash g_is31_leds[DRIVER_LED_TOTAL] = {
const is31_led PROGMEM g_is31_leds[DRIVER_LED_TOTAL] = {
/* Refer to IS31 manual for these locations
* driver
* | R location
@@ -414,7 +414,7 @@ const is31_led __flash g_is31_leds[DRIVER_LED_TOTAL] = {
#define ISSI_ADDR_2 0x76 // 11101[10] <- SDA
#define ISSI_ADDR_3 0x75 // 11101[01] <- SCL
const is31_led __flash g_is31_leds[DRIVER_LED_TOTAL] = {
const is31_led PROGMEM g_is31_leds[DRIVER_LED_TOTAL] = {
/* Refer to IS31 manual for these locations
* driver
* | R location
@@ -541,7 +541,7 @@ const is31_led __flash g_is31_leds[DRIVER_LED_TOTAL] = {
#define ISSI_ADDR_1 0x74
#define ISSI_ADDR_2 0x76
const is31_led __flash g_is31_leds[DRIVER_LED_TOTAL] = {
const is31_led PROGMEM g_is31_leds[DRIVER_LED_TOTAL] = {
/* Refer to IS31 manual for these locations
* driver
* | R location
@@ -622,7 +622,7 @@ const is31_led __flash g_is31_leds[DRIVER_LED_TOTAL] = {
#define ISSI_ADDR_1 0x74
#define ISSI_ADDR_2 0x77
const is31_led __flash g_is31_leds[DRIVER_LED_TOTAL] = {
const is31_led PROGMEM g_is31_leds[DRIVER_LED_TOTAL] = {
/* Refer to IS31 manual for these locations
* driver
* | R location
@@ -709,7 +709,7 @@ const is31_led __flash g_is31_leds[DRIVER_LED_TOTAL] = {
#define ISSI_ADDR_1 0x74
#define ISSI_ADDR_2
const is31_led __flash g_is31_leds[DRIVER_LED_TOTAL] = {
const is31_led PROGMEM g_is31_leds[DRIVER_LED_TOTAL] = {
{0, C1_9, C3_10, C4_10}, // LB1
{0, C1_10, C2_10, C4_11}, // LB2
{0, C1_11, C2_11, C3_11}, // LB3
@@ -729,7 +729,7 @@ const is31_led __flash g_is31_leds[DRIVER_LED_TOTAL] = {
#define ISSI_ADDR_1 0x74
#define ISSI_ADDR_2 0x76
const is31_led __flash g_is31_leds[DRIVER_LED_TOTAL] = {
const is31_led PROGMEM g_is31_leds[DRIVER_LED_TOTAL] = {
/* Refer to IS31 manual for these locations
* driver
* | R location

687
platforms/chibios/eeprom_stm32.c Normal file
View File

@@ -0,0 +1,687 @@
/*
* This software is experimental and a work in progress.
* Under no circumstances should these files be used in relation to any critical system(s).
* Use of these files is at your own risk.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
* INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
* PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE
* LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*
* This files are free to use from http://engsta.com/stm32-flash-memory-eeprom-emulator/ by
* Artur F.
*
* Modifications for QMK and STM32F303 by Yiancar
* Modifications to add flash wear leveling by Ilya Zhuravlev
* Modifications to increase flash density by Don Kjer
*/
#include <stdio.h>
#include <stdbool.h>
#include "util.h"
#include "debug.h"
#include "eeprom_stm32.h"
#include "flash_stm32.h"
/*
* We emulate eeprom by writing a snapshot compacted view of eeprom contents,
* followed by a write log of any change since that snapshot:
*
* === SIMULATED EEPROM CONTENTS ===
*
* ┌─ Compacted ┬ Write Log ─┐
* │............│[BYTE][BYTE]│
* │FFFF....FFFF│[WRD0][WRD1]│
* │FFFFFFFFFFFF│[WORD][NEXT]│
* │....FFFFFFFF│[BYTE][WRD0]│
* ├────────────┼────────────┤
* └──PAGE_BASE │ │
* PAGE_LAST─┴─WRITE_BASE │
* WRITE_LAST ┘
*
* Compacted contents are the 1's complement of the actual EEPROM contents.
* e.g. An 'FFFF' represents a '0000' value.
*
* The size of the 'compacted' area is equal to the size of the 'emulated' eeprom.
* The size of the compacted-area and write log are configurable, and the combined
* size of Compacted + WriteLog is a multiple FEE_PAGE_SIZE, which is MCU dependent.
* Simulated Eeprom contents are located at the end of available flash space.
*
* The following configuration defines can be set:
*
* FEE_PAGE_COUNT # Total number of pages to use for eeprom simulation (Compact + Write log)
* FEE_DENSITY_BYTES # Size of simulated eeprom. (Defaults to half the space allocated by FEE_PAGE_COUNT)
* NOTE: The current implementation does not include page swapping,
* and FEE_DENSITY_BYTES will consume that amount of RAM as a cached view of actual EEPROM contents.
*
* The maximum size of FEE_DENSITY_BYTES is currently 16384. The write log size equals
* FEE_PAGE_COUNT * FEE_PAGE_SIZE - FEE_DENSITY_BYTES.
* The larger the write log, the less frequently the compacted area needs to be rewritten.
*
*
* *** General Algorithm ***
*
* During initialization:
* The contents of the Compacted-flash area are loaded and the 1's complement value
* is cached into memory (e.g. 0xFFFF in Flash represents 0x0000 in cache).
* Write log entries are processed until a 0xFFFF is reached.
* Each log entry updates a byte or word in the cache.
*
* During reads:
* EEPROM contents are given back directly from the cache in memory.
*
* During writes:
* The contents of the cache is updated first.
* If the Compacted-flash area corresponding to the write address is unprogrammed, the 1's complement of the value is written directly into Compacted-flash
* Otherwise:
* If the write log is full, erase both the Compacted-flash area and the Write log, then write cached contents to the Compacted-flash area.
* Otherwise a Write log entry is constructed and appended to the next free position in the Write log.
*
*
* *** Write Log Structure ***
*
* Write log entries allow for optimized byte writes to addresses below 128. Writing 0 or 1 words are also optimized when word-aligned.
*
* === WRITE LOG ENTRY FORMATS ===
*
* ╔═══ Byte-Entry ══╗
* ║0XXXXXXX║YYYYYYYY║
* ║ └──┬──┘║└──┬───┘║
* ║ Address║ Value ║
* ╚════════╩════════╝
* 0 <= Address < 0x80 (128)
*
* ╔ Word-Encoded 0 ╗
* ║100XXXXXXXXXXXXX║
* ║ │└─────┬─────┘║
* ║ │Address >> 1 ║
* ║ └── Value: 0 ║
* ╚════════════════╝
* 0 <= Address <= 0x3FFE (16382)
*
* ╔ Word-Encoded 1 ╗
* ║101XXXXXXXXXXXXX║
* ║ │└─────┬─────┘║
* ║ │Address >> 1 ║
* ║ └── Value: 1 ║
* ╚════════════════╝
* 0 <= Address <= 0x3FFE (16382)
*
* ╔═══ Reserved ═══╗
* ║110XXXXXXXXXXXXX║
* ╚════════════════╝
*
* ╔═══════════ Word-Next ═══════════╗
* ║111XXXXXXXXXXXXX║YYYYYYYYYYYYYYYY║
* ║ └─────┬─────┘║└───────┬──────┘║
* ║(Address-128)>>1║ ~Value ║
* ╚════════════════╩════════════════╝
* ( 0 <= Address < 0x0080 (128): Reserved)
* 0x80 <= Address <= 0x3FFE (16382)
*
* Write Log entry ranges:
* 0x0000 ... 0x7FFF - Byte-Entry; address is (Entry & 0x7F00) >> 4; value is (Entry & 0xFF)
* 0x8000 ... 0x9FFF - Word-Encoded 0; address is (Entry & 0x1FFF) << 1; value is 0
* 0xA000 ... 0xBFFF - Word-Encoded 1; address is (Entry & 0x1FFF) << 1; value is 1
* 0xC000 ... 0xDFFF - Reserved
* 0xE000 ... 0xFFBF - Word-Next; address is (Entry & 0x1FFF) << 1 + 0x80; value is ~(Next_Entry)
* 0xFFC0 ... 0xFFFE - Reserved
* 0xFFFF - Unprogrammed
*
*/
#include "eeprom_stm32_defs.h"
#if !defined(FEE_PAGE_SIZE) || !defined(FEE_PAGE_COUNT) || !defined(FEE_MCU_FLASH_SIZE) || !defined(FEE_PAGE_BASE_ADDRESS)
# error "not implemented."
#endif
/* These bits are used for optimizing encoding of bytes, 0 and 1 */
#define FEE_WORD_ENCODING 0x8000
#define FEE_VALUE_NEXT 0x6000
#define FEE_VALUE_RESERVED 0x4000
#define FEE_VALUE_ENCODED 0x2000
#define FEE_BYTE_RANGE 0x80
/* Addressable range 16KByte: 0 <-> (0x1FFF << 1) */
#define FEE_ADDRESS_MAX_SIZE 0x4000
/* Flash word value after erase */
#define FEE_EMPTY_WORD ((uint16_t)0xFFFF)
/* Size of combined compacted eeprom and write log pages */
#define FEE_DENSITY_MAX_SIZE (FEE_PAGE_COUNT * FEE_PAGE_SIZE)
#ifndef FEE_MCU_FLASH_SIZE_IGNORE_CHECK /* *TODO: Get rid of this check */
# if FEE_DENSITY_MAX_SIZE > (FEE_MCU_FLASH_SIZE * 1024)
# pragma message STR(FEE_DENSITY_MAX_SIZE) " > " STR(FEE_MCU_FLASH_SIZE * 1024)
# error emulated eeprom: FEE_DENSITY_MAX_SIZE is greater than available flash size
# endif
#endif
/* Size of emulated eeprom */
#ifdef FEE_DENSITY_BYTES
# if (FEE_DENSITY_BYTES > FEE_DENSITY_MAX_SIZE)
# pragma message STR(FEE_DENSITY_BYTES) " > " STR(FEE_DENSITY_MAX_SIZE)
# error emulated eeprom: FEE_DENSITY_BYTES exceeds FEE_DENSITY_MAX_SIZE
# endif
# if (FEE_DENSITY_BYTES == FEE_DENSITY_MAX_SIZE)
# pragma message STR(FEE_DENSITY_BYTES) " == " STR(FEE_DENSITY_MAX_SIZE)
# warning emulated eeprom: FEE_DENSITY_BYTES leaves no room for a write log. This will greatly increase the flash wear rate!
# endif
# if FEE_DENSITY_BYTES > FEE_ADDRESS_MAX_SIZE
# pragma message STR(FEE_DENSITY_BYTES) " > " STR(FEE_ADDRESS_MAX_SIZE)
# error emulated eeprom: FEE_DENSITY_BYTES is greater than FEE_ADDRESS_MAX_SIZE allows
# endif
# if ((FEE_DENSITY_BYTES) % 2) == 1
# error emulated eeprom: FEE_DENSITY_BYTES must be even
# endif
#else
/* Default to half of allocated space used for emulated eeprom, half for write log */
# define FEE_DENSITY_BYTES (FEE_PAGE_COUNT * FEE_PAGE_SIZE / 2)
#endif
/* Size of write log */
#ifdef FEE_WRITE_LOG_BYTES
# if ((FEE_DENSITY_BYTES + FEE_WRITE_LOG_BYTES) > FEE_DENSITY_MAX_SIZE)
# pragma message STR(FEE_DENSITY_BYTES) " + " STR(FEE_WRITE_LOG_BYTES) " > " STR(FEE_DENSITY_MAX_SIZE)
# error emulated eeprom: FEE_WRITE_LOG_BYTES exceeds remaining FEE_DENSITY_MAX_SIZE
# endif
# if ((FEE_WRITE_LOG_BYTES) % 2) == 1
# error emulated eeprom: FEE_WRITE_LOG_BYTES must be even
# endif
#else
/* Default to use all remaining space */
# define FEE_WRITE_LOG_BYTES (FEE_PAGE_COUNT * FEE_PAGE_SIZE - FEE_DENSITY_BYTES)
#endif
/* Start of the emulated eeprom compacted flash area */
#define FEE_COMPACTED_BASE_ADDRESS FEE_PAGE_BASE_ADDRESS
/* End of the emulated eeprom compacted flash area */
#define FEE_COMPACTED_LAST_ADDRESS (FEE_COMPACTED_BASE_ADDRESS + FEE_DENSITY_BYTES)
/* Start of the emulated eeprom write log */
#define FEE_WRITE_LOG_BASE_ADDRESS FEE_COMPACTED_LAST_ADDRESS
/* End of the emulated eeprom write log */
#define FEE_WRITE_LOG_LAST_ADDRESS (FEE_WRITE_LOG_BASE_ADDRESS + FEE_WRITE_LOG_BYTES)
#if defined(DYNAMIC_KEYMAP_EEPROM_MAX_ADDR) && (DYNAMIC_KEYMAP_EEPROM_MAX_ADDR >= FEE_DENSITY_BYTES)
# error emulated eeprom: DYNAMIC_KEYMAP_EEPROM_MAX_ADDR is greater than the FEE_DENSITY_BYTES available
#endif
/* In-memory contents of emulated eeprom for faster access */
/* *TODO: Implement page swapping */
static uint16_t WordBuf[FEE_DENSITY_BYTES / 2];
static uint8_t *DataBuf = (uint8_t *)WordBuf;
/* Pointer to the first available slot within the write log */
static uint16_t *empty_slot;
// #define DEBUG_EEPROM_OUTPUT
/*
* Debug print utils
*/
#if defined(DEBUG_EEPROM_OUTPUT)
# define debug_eeprom debug_enable
# define eeprom_println(s) println(s)
# define eeprom_printf(fmt, ...) xprintf(fmt, ##__VA_ARGS__);
#else /* NO_DEBUG */
# define debug_eeprom false
# define eeprom_println(s)
# define eeprom_printf(fmt, ...)
#endif /* NO_DEBUG */
void print_eeprom(void) {
#ifndef NO_DEBUG
int empty_rows = 0;
for (uint16_t i = 0; i < FEE_DENSITY_BYTES; i++) {
if (i % 16 == 0) {
if (i >= FEE_DENSITY_BYTES - 16) {
/* Make sure we display the last row */
empty_rows = 0;
}
/* Check if this row is uninitialized */
++empty_rows;
for (uint16_t j = 0; j < 16; j++) {
if (DataBuf[i + j]) {
empty_rows = 0;
break;
}
}
if (empty_rows > 1) {
/* Repeat empty row */
if (empty_rows == 2) {
/* Only display the first repeat empty row */
println("*");
}
i += 15;
continue;
}
xprintf("%04x", i);
}
if (i % 8 == 0) print(" ");
xprintf(" %02x", DataBuf[i]);
if ((i + 1) % 16 == 0) {
println("");
}
}
#endif
}
uint16_t EEPROM_Init(void) {
/* Load emulated eeprom contents from compacted flash into memory */
uint16_t *src = (uint16_t *)FEE_COMPACTED_BASE_ADDRESS;
uint16_t *dest = (uint16_t *)DataBuf;
for (; src < (uint16_t *)FEE_COMPACTED_LAST_ADDRESS; ++src, ++dest) {
*dest = ~*src;
}
if (debug_eeprom) {
println("EEPROM_Init Compacted Pages:");
print_eeprom();
println("EEPROM_Init Write Log:");
}
/* Replay write log */
uint16_t *log_addr;
for (log_addr = (uint16_t *)FEE_WRITE_LOG_BASE_ADDRESS; log_addr < (uint16_t *)FEE_WRITE_LOG_LAST_ADDRESS; ++log_addr) {
uint16_t address = *log_addr;
if (address == FEE_EMPTY_WORD) {
break;
}
/* Check for lowest 128-bytes optimization */
if (!(address & FEE_WORD_ENCODING)) {
uint8_t bvalue = (uint8_t)address;
address >>= 8;
DataBuf[address] = bvalue;
eeprom_printf("DataBuf[0x%02x] = 0x%02x;\n", address, bvalue);
} else {
uint16_t wvalue;
/* Check if value is in next word */
if ((address & FEE_VALUE_NEXT) == FEE_VALUE_NEXT) {
/* Read value from next word */
if (++log_addr >= (uint16_t *)FEE_WRITE_LOG_LAST_ADDRESS) {
break;
}
wvalue = ~*log_addr;
if (!wvalue) {
eeprom_printf("Incomplete write at log_addr: 0x%04x;\n", (uint32_t)log_addr);
/* Possibly incomplete write. Ignore and continue */
continue;
}
address &= 0x1FFF;
address <<= 1;
/* Writes to addresses less than 128 are byte log entries */
address += FEE_BYTE_RANGE;
} else {
/* Reserved for future use */
if (address & FEE_VALUE_RESERVED) {
eeprom_printf("Reserved encoded value at log_addr: 0x%04x;\n", (uint32_t)log_addr);
continue;
}
/* Optimization for 0 or 1 values. */
wvalue = (address & FEE_VALUE_ENCODED) >> 13;
address &= 0x1FFF;
address <<= 1;
}
if (address < FEE_DENSITY_BYTES) {
eeprom_printf("DataBuf[0x%04x] = 0x%04x;\n", address, wvalue);
*(uint16_t *)(&DataBuf[address]) = wvalue;
} else {
eeprom_printf("DataBuf[0x%04x] cannot be set to 0x%04x [BAD ADDRESS]\n", address, wvalue);
}
}
}
empty_slot = log_addr;
if (debug_eeprom) {
println("EEPROM_Init Final DataBuf:");
print_eeprom();
}
return FEE_DENSITY_BYTES;
}
/* Clear flash contents (doesn't touch in-memory DataBuf) */
static void eeprom_clear(void) {
FLASH_Unlock();
for (uint16_t page_num = 0; page_num < FEE_PAGE_COUNT; ++page_num) {
eeprom_printf("FLASH_ErasePage(0x%04x)\n", (uint32_t)(FEE_PAGE_BASE_ADDRESS + (page_num * FEE_PAGE_SIZE)));
FLASH_ErasePage(FEE_PAGE_BASE_ADDRESS + (page_num * FEE_PAGE_SIZE));
}
FLASH_Lock();
empty_slot = (uint16_t *)FEE_WRITE_LOG_BASE_ADDRESS;
eeprom_printf("eeprom_clear empty_slot: 0x%08x\n", (uint32_t)empty_slot);
}
/* Erase emulated eeprom */
void EEPROM_Erase(void) {
eeprom_println("EEPROM_Erase");
/* Erase compacted pages and write log */
eeprom_clear();
/* re-initialize to reset DataBuf */
EEPROM_Init();
}
/* Compact write log */
static uint8_t eeprom_compact(void) {
/* Erase compacted pages and write log */
eeprom_clear();
FLASH_Unlock();
FLASH_Status final_status = FLASH_COMPLETE;
/* Write emulated eeprom contents from memory to compacted flash */
uint16_t *src = (uint16_t *)DataBuf;
uintptr_t dest = FEE_COMPACTED_BASE_ADDRESS;
uint16_t value;
for (; dest < FEE_COMPACTED_LAST_ADDRESS; ++src, dest += 2) {
value = *src;
if (value) {
eeprom_printf("FLASH_ProgramHalfWord(0x%04x, 0x%04x)\n", (uint32_t)dest, ~value);
FLASH_Status status = FLASH_ProgramHalfWord(dest, ~value);
if (status != FLASH_COMPLETE) final_status = status;
}
}
FLASH_Lock();
if (debug_eeprom) {
println("eeprom_compacted:");
print_eeprom();
}
return final_status;
}
static uint8_t eeprom_write_direct_entry(uint16_t Address) {
/* Check if we can just write this directly to the compacted flash area */
uintptr_t directAddress = FEE_COMPACTED_BASE_ADDRESS + (Address & 0xFFFE);
if (*(uint16_t *)directAddress == FEE_EMPTY_WORD) {
/* Write the value directly to the compacted area without a log entry */
uint16_t value = ~*(uint16_t *)(&DataBuf[Address & 0xFFFE]);
/* Early exit if a write isn't needed */
if (value == FEE_EMPTY_WORD) return FLASH_COMPLETE;
FLASH_Unlock();
eeprom_printf("FLASH_ProgramHalfWord(0x%08x, 0x%04x) [DIRECT]\n", (uint32_t)directAddress, value);
FLASH_Status status = FLASH_ProgramHalfWord(directAddress, value);
FLASH_Lock();
return status;
}
return 0;
}
static uint8_t eeprom_write_log_word_entry(uint16_t Address) {
FLASH_Status final_status = FLASH_COMPLETE;
uint16_t value = *(uint16_t *)(&DataBuf[Address]);
eeprom_printf("eeprom_write_log_word_entry(0x%04x): 0x%04x\n", Address, value);
/* MSB signifies the lowest 128-byte optimization is not in effect */
uint16_t encoding = FEE_WORD_ENCODING;
uint8_t entry_size;
if (value <= 1) {
encoding |= value << 13;
entry_size = 2;
} else {
encoding |= FEE_VALUE_NEXT;
entry_size = 4;
/* Writes to addresses less than 128 are byte log entries */
Address -= FEE_BYTE_RANGE;
}
/* if we can't find an empty spot, we must compact emulated eeprom */
if (empty_slot > (uint16_t *)(FEE_WRITE_LOG_LAST_ADDRESS - entry_size)) {
/* compact the write log into the compacted flash area */
return eeprom_compact();
}
/* Word log writes should be word-aligned. Take back a bit */
Address >>= 1;
Address |= encoding;
/* ok we found a place let's write our data */
FLASH_Unlock();
/* address */
eeprom_printf("FLASH_ProgramHalfWord(0x%08x, 0x%04x)\n", (uint32_t)empty_slot, Address);
final_status = FLASH_ProgramHalfWord((uintptr_t)empty_slot++, Address);
/* value */
if (encoding == (FEE_WORD_ENCODING | FEE_VALUE_NEXT)) {
eeprom_printf("FLASH_ProgramHalfWord(0x%08x, 0x%04x)\n", (uint32_t)empty_slot, ~value);
FLASH_Status status = FLASH_ProgramHalfWord((uintptr_t)empty_slot++, ~value);
if (status != FLASH_COMPLETE) final_status = status;
}
FLASH_Lock();
return final_status;
}
static uint8_t eeprom_write_log_byte_entry(uint16_t Address) {
eeprom_printf("eeprom_write_log_byte_entry(0x%04x): 0x%02x\n", Address, DataBuf[Address]);
/* if couldn't find an empty spot, we must compact emulated eeprom */
if (empty_slot >= (uint16_t *)FEE_WRITE_LOG_LAST_ADDRESS) {
/* compact the write log into the compacted flash area */
return eeprom_compact();
}
/* ok we found a place let's write our data */
FLASH_Unlock();
/* Pack address and value into the same word */
uint16_t value = (Address << 8) | DataBuf[Address];
/* write to flash */
eeprom_printf("FLASH_ProgramHalfWord(0x%08x, 0x%04x)\n", (uint32_t)empty_slot, value);
FLASH_Status status = FLASH_ProgramHalfWord((uintptr_t)empty_slot++, value);
FLASH_Lock();
return status;
}
uint8_t EEPROM_WriteDataByte(uint16_t Address, uint8_t DataByte) {
/* if the address is out-of-bounds, do nothing */
if (Address >= FEE_DENSITY_BYTES) {
eeprom_printf("EEPROM_WriteDataByte(0x%04x, 0x%02x) [BAD ADDRESS]\n", Address, DataByte);
return FLASH_BAD_ADDRESS;
}
/* if the value is the same, don't bother writing it */
if (DataBuf[Address] == DataByte) {
eeprom_printf("EEPROM_WriteDataByte(0x%04x, 0x%02x) [SKIP SAME]\n", Address, DataByte);
return 0;
}
/* keep DataBuf cache in sync */
DataBuf[Address] = DataByte;
eeprom_printf("EEPROM_WriteDataByte DataBuf[0x%04x] = 0x%02x\n", Address, DataBuf[Address]);
/* perform the write into flash memory */
/* First, attempt to write directly into the compacted flash area */
FLASH_Status status = eeprom_write_direct_entry(Address);
if (!status) {
/* Otherwise append to the write log */
if (Address < FEE_BYTE_RANGE) {
status = eeprom_write_log_byte_entry(Address);
} else {
status = eeprom_write_log_word_entry(Address & 0xFFFE);
}
}
if (status != 0 && status != FLASH_COMPLETE) {
eeprom_printf("EEPROM_WriteDataByte [STATUS == %d]\n", status);
}
return status;
}
uint8_t EEPROM_WriteDataWord(uint16_t Address, uint16_t DataWord) {
/* if the address is out-of-bounds, do nothing */
if (Address >= FEE_DENSITY_BYTES) {
eeprom_printf("EEPROM_WriteDataWord(0x%04x, 0x%04x) [BAD ADDRESS]\n", Address, DataWord);
return FLASH_BAD_ADDRESS;
}
/* Check for word alignment */
FLASH_Status final_status = FLASH_COMPLETE;
if (Address % 2) {
final_status = EEPROM_WriteDataByte(Address, DataWord);
FLASH_Status status = EEPROM_WriteDataByte(Address + 1, DataWord >> 8);
if (status != FLASH_COMPLETE) final_status = status;
if (final_status != 0 && final_status != FLASH_COMPLETE) {
eeprom_printf("EEPROM_WriteDataWord [STATUS == %d]\n", final_status);
}
return final_status;
}
/* if the value is the same, don't bother writing it */
uint16_t oldValue = *(uint16_t *)(&DataBuf[Address]);
if (oldValue == DataWord) {
eeprom_printf("EEPROM_WriteDataWord(0x%04x, 0x%04x) [SKIP SAME]\n", Address, DataWord);
return 0;
}
/* keep DataBuf cache in sync */
*(uint16_t *)(&DataBuf[Address]) = DataWord;
eeprom_printf("EEPROM_WriteDataWord DataBuf[0x%04x] = 0x%04x\n", Address, *(uint16_t *)(&DataBuf[Address]));
/* perform the write into flash memory */
/* First, attempt to write directly into the compacted flash area */
final_status = eeprom_write_direct_entry(Address);
if (!final_status) {
/* Otherwise append to the write log */
/* Check if we need to fall back to byte write */
if (Address < FEE_BYTE_RANGE) {
final_status = FLASH_COMPLETE;
/* Only write a byte if it has changed */
if ((uint8_t)oldValue != (uint8_t)DataWord) {
final_status = eeprom_write_log_byte_entry(Address);
}
FLASH_Status status = FLASH_COMPLETE;
/* Only write a byte if it has changed */
if ((oldValue >> 8) != (DataWord >> 8)) {
status = eeprom_write_log_byte_entry(Address + 1);
}
if (status != FLASH_COMPLETE) final_status = status;
} else {
final_status = eeprom_write_log_word_entry(Address);
}
}
if (final_status != 0 && final_status != FLASH_COMPLETE) {
eeprom_printf("EEPROM_WriteDataWord [STATUS == %d]\n", final_status);
}
return final_status;
}
uint8_t EEPROM_ReadDataByte(uint16_t Address) {
uint8_t DataByte = 0xFF;
if (Address < FEE_DENSITY_BYTES) {
DataByte = DataBuf[Address];
}
eeprom_printf("EEPROM_ReadDataByte(0x%04x): 0x%02x\n", Address, DataByte);
return DataByte;
}
uint16_t EEPROM_ReadDataWord(uint16_t Address) {
uint16_t DataWord = 0xFFFF;
if (Address < FEE_DENSITY_BYTES - 1) {
/* Check word alignment */
if (Address % 2) {
DataWord = DataBuf[Address] | (DataBuf[Address + 1] << 8);
} else {
DataWord = *(uint16_t *)(&DataBuf[Address]);
}
}
eeprom_printf("EEPROM_ReadDataWord(0x%04x): 0x%04x\n", Address, DataWord);
return DataWord;
}
/*****************************************************************************
* Bind to eeprom_driver.c
*******************************************************************************/
void eeprom_driver_init(void) { EEPROM_Init(); }
void eeprom_driver_erase(void) { EEPROM_Erase(); }
void eeprom_read_block(void *buf, const void *addr, size_t len) {
const uint8_t *src = (const uint8_t *)addr;
uint8_t * dest = (uint8_t *)buf;
/* Check word alignment */
if (len && (uintptr_t)src % 2) {
/* Read the unaligned first byte */
*dest++ = EEPROM_ReadDataByte((const uintptr_t)src++);
--len;
}
uint16_t value;
bool aligned = ((uintptr_t)dest % 2 == 0);
while (len > 1) {
value = EEPROM_ReadDataWord((const uintptr_t)((uint16_t *)src));
if (aligned) {
*(uint16_t *)dest = value;
dest += 2;
} else {
*dest++ = value;
*dest++ = value >> 8;
}
src += 2;
len -= 2;
}
if (len) {
*dest = EEPROM_ReadDataByte((const uintptr_t)src);
}
}
void eeprom_write_block(const void *buf, void *addr, size_t len) {
uint8_t * dest = (uint8_t *)addr;
const uint8_t *src = (const uint8_t *)buf;
/* Check word alignment */
if (len && (uintptr_t)dest % 2) {
/* Write the unaligned first byte */
EEPROM_WriteDataByte((uintptr_t)dest++, *src++);
--len;
}
uint16_t value;
bool aligned = ((uintptr_t)src % 2 == 0);
while (len > 1) {
if (aligned) {
value = *(uint16_t *)src;
} else {
value = *(uint8_t *)src | (*(uint8_t *)(src + 1) << 8);
}
EEPROM_WriteDataWord((uintptr_t)((uint16_t *)dest), value);
dest += 2;
src += 2;
len -= 2;
}
if (len) {
EEPROM_WriteDataByte((uintptr_t)dest, *src);
}
}

Some files were not shown because too many files have changed in this diff Show More